block/export: Add query-block-exports
[qemu.git] / include / hw / arm / xlnx-versal.h
1 /*
2 * Model of the Xilinx Versal
3 *
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 #ifndef XLNX_VERSAL_H
13 #define XLNX_VERSAL_H
14
15 #include "hw/sysbus.h"
16 #include "hw/arm/boot.h"
17 #include "hw/sd/sdhci.h"
18 #include "hw/intc/arm_gicv3.h"
19 #include "hw/char/pl011.h"
20 #include "hw/dma/xlnx-zdma.h"
21 #include "hw/net/cadence_gem.h"
22 #include "hw/rtc/xlnx-zynqmp-rtc.h"
23 #include "qom/object.h"
24
25 #define TYPE_XLNX_VERSAL "xlnx-versal"
26 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
27
28 #define XLNX_VERSAL_NR_ACPUS 2
29 #define XLNX_VERSAL_NR_UARTS 2
30 #define XLNX_VERSAL_NR_GEMS 2
31 #define XLNX_VERSAL_NR_ADMAS 8
32 #define XLNX_VERSAL_NR_SDS 2
33 #define XLNX_VERSAL_NR_IRQS 192
34
35 struct Versal {
36 /*< private >*/
37 SysBusDevice parent_obj;
38
39 /*< public >*/
40 struct {
41 struct {
42 MemoryRegion mr;
43 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
44 GICv3State gic;
45 } apu;
46 } fpd;
47
48 MemoryRegion mr_ps;
49
50 struct {
51 /* 4 ranges to access DDR. */
52 MemoryRegion mr_ddr_ranges[4];
53 } noc;
54
55 struct {
56 MemoryRegion mr_ocm;
57
58 struct {
59 PL011State uart[XLNX_VERSAL_NR_UARTS];
60 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
61 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
62 } iou;
63 } lpd;
64
65 /* The Platform Management Controller subsystem. */
66 struct {
67 struct {
68 SDHCIState sd[XLNX_VERSAL_NR_SDS];
69 } iou;
70
71 XlnxZynqMPRTC rtc;
72 } pmc;
73
74 struct {
75 MemoryRegion *mr_ddr;
76 uint32_t psci_conduit;
77 } cfg;
78 };
79
80 /* Memory-map and IRQ definitions. Copied a subset from
81 * auto-generated files. */
82
83 #define VERSAL_GIC_MAINT_IRQ 9
84 #define VERSAL_TIMER_VIRT_IRQ 11
85 #define VERSAL_TIMER_S_EL1_IRQ 13
86 #define VERSAL_TIMER_NS_EL1_IRQ 14
87 #define VERSAL_TIMER_NS_EL2_IRQ 10
88
89 #define VERSAL_UART0_IRQ_0 18
90 #define VERSAL_UART1_IRQ_0 19
91 #define VERSAL_GEM0_IRQ_0 56
92 #define VERSAL_GEM0_WAKE_IRQ_0 57
93 #define VERSAL_GEM1_IRQ_0 58
94 #define VERSAL_GEM1_WAKE_IRQ_0 59
95 #define VERSAL_ADMA_IRQ_0 60
96 #define VERSAL_RTC_APB_ERR_IRQ 121
97 #define VERSAL_SD0_IRQ_0 126
98 #define VERSAL_RTC_ALARM_IRQ 142
99 #define VERSAL_RTC_SECONDS_IRQ 143
100
101 /* Architecturally reserved IRQs suitable for virtualization. */
102 #define VERSAL_RSVD_IRQ_FIRST 111
103 #define VERSAL_RSVD_IRQ_LAST 118
104
105 #define MM_TOP_RSVD 0xa0000000U
106 #define MM_TOP_RSVD_SIZE 0x4000000
107 #define MM_GIC_APU_DIST_MAIN 0xf9000000U
108 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
109 #define MM_GIC_APU_REDIST_0 0xf9080000U
110 #define MM_GIC_APU_REDIST_0_SIZE 0x80000
111
112 #define MM_UART0 0xff000000U
113 #define MM_UART0_SIZE 0x10000
114 #define MM_UART1 0xff010000U
115 #define MM_UART1_SIZE 0x10000
116
117 #define MM_GEM0 0xff0c0000U
118 #define MM_GEM0_SIZE 0x10000
119 #define MM_GEM1 0xff0d0000U
120 #define MM_GEM1_SIZE 0x10000
121
122 #define MM_ADMA_CH0 0xffa80000U
123 #define MM_ADMA_CH0_SIZE 0x10000
124
125 #define MM_OCM 0xfffc0000U
126 #define MM_OCM_SIZE 0x40000
127
128 #define MM_TOP_DDR 0x0
129 #define MM_TOP_DDR_SIZE 0x80000000U
130 #define MM_TOP_DDR_2 0x800000000ULL
131 #define MM_TOP_DDR_2_SIZE 0x800000000ULL
132 #define MM_TOP_DDR_3 0xc000000000ULL
133 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL
134 #define MM_TOP_DDR_4 0x10000000000ULL
135 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL
136
137 #define MM_PSM_START 0xffc80000U
138 #define MM_PSM_END 0xffcf0000U
139
140 #define MM_CRL 0xff5e0000U
141 #define MM_CRL_SIZE 0x300000
142 #define MM_IOU_SCNTR 0xff130000U
143 #define MM_IOU_SCNTR_SIZE 0x10000
144 #define MM_IOU_SCNTRS 0xff140000U
145 #define MM_IOU_SCNTRS_SIZE 0x10000
146 #define MM_FPD_CRF 0xfd1a0000U
147 #define MM_FPD_CRF_SIZE 0x140000
148
149 #define MM_PMC_SD0 0xf1040000U
150 #define MM_PMC_SD0_SIZE 0x10000
151 #define MM_PMC_CRP 0xf1260000U
152 #define MM_PMC_CRP_SIZE 0x10000
153 #define MM_PMC_RTC 0xf12a0000
154 #define MM_PMC_RTC_SIZE 0x10000
155 #endif