ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / arm / xlnx-versal.h
1 /*
2 * Model of the Xilinx Versal
3 *
4 * Copyright (c) 2018 Xilinx Inc.
5 * Written by Edgar E. Iglesias
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 #ifndef XLNX_VERSAL_H
13 #define XLNX_VERSAL_H
14
15 #include "hw/sysbus.h"
16 #include "hw/arm/boot.h"
17 #include "hw/sd/sdhci.h"
18 #include "hw/intc/arm_gicv3.h"
19 #include "hw/char/pl011.h"
20 #include "hw/dma/xlnx-zdma.h"
21 #include "hw/net/cadence_gem.h"
22 #include "hw/rtc/xlnx-zynqmp-rtc.h"
23
24 #define TYPE_XLNX_VERSAL "xlnx-versal"
25 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
26
27 #define XLNX_VERSAL_NR_ACPUS 2
28 #define XLNX_VERSAL_NR_UARTS 2
29 #define XLNX_VERSAL_NR_GEMS 2
30 #define XLNX_VERSAL_NR_ADMAS 8
31 #define XLNX_VERSAL_NR_SDS 2
32 #define XLNX_VERSAL_NR_IRQS 192
33
34 typedef struct Versal {
35 /*< private >*/
36 SysBusDevice parent_obj;
37
38 /*< public >*/
39 struct {
40 struct {
41 MemoryRegion mr;
42 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
43 GICv3State gic;
44 } apu;
45 } fpd;
46
47 MemoryRegion mr_ps;
48
49 struct {
50 /* 4 ranges to access DDR. */
51 MemoryRegion mr_ddr_ranges[4];
52 } noc;
53
54 struct {
55 MemoryRegion mr_ocm;
56
57 struct {
58 PL011State uart[XLNX_VERSAL_NR_UARTS];
59 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
60 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
61 } iou;
62 } lpd;
63
64 /* The Platform Management Controller subsystem. */
65 struct {
66 struct {
67 SDHCIState sd[XLNX_VERSAL_NR_SDS];
68 } iou;
69
70 XlnxZynqMPRTC rtc;
71 } pmc;
72
73 struct {
74 MemoryRegion *mr_ddr;
75 uint32_t psci_conduit;
76 } cfg;
77 } Versal;
78
79 /* Memory-map and IRQ definitions. Copied a subset from
80 * auto-generated files. */
81
82 #define VERSAL_GIC_MAINT_IRQ 9
83 #define VERSAL_TIMER_VIRT_IRQ 11
84 #define VERSAL_TIMER_S_EL1_IRQ 13
85 #define VERSAL_TIMER_NS_EL1_IRQ 14
86 #define VERSAL_TIMER_NS_EL2_IRQ 10
87
88 #define VERSAL_UART0_IRQ_0 18
89 #define VERSAL_UART1_IRQ_0 19
90 #define VERSAL_GEM0_IRQ_0 56
91 #define VERSAL_GEM0_WAKE_IRQ_0 57
92 #define VERSAL_GEM1_IRQ_0 58
93 #define VERSAL_GEM1_WAKE_IRQ_0 59
94 #define VERSAL_ADMA_IRQ_0 60
95 #define VERSAL_RTC_APB_ERR_IRQ 121
96 #define VERSAL_SD0_IRQ_0 126
97 #define VERSAL_RTC_ALARM_IRQ 142
98 #define VERSAL_RTC_SECONDS_IRQ 143
99
100 /* Architecturally reserved IRQs suitable for virtualization. */
101 #define VERSAL_RSVD_IRQ_FIRST 111
102 #define VERSAL_RSVD_IRQ_LAST 118
103
104 #define MM_TOP_RSVD 0xa0000000U
105 #define MM_TOP_RSVD_SIZE 0x4000000
106 #define MM_GIC_APU_DIST_MAIN 0xf9000000U
107 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
108 #define MM_GIC_APU_REDIST_0 0xf9080000U
109 #define MM_GIC_APU_REDIST_0_SIZE 0x80000
110
111 #define MM_UART0 0xff000000U
112 #define MM_UART0_SIZE 0x10000
113 #define MM_UART1 0xff010000U
114 #define MM_UART1_SIZE 0x10000
115
116 #define MM_GEM0 0xff0c0000U
117 #define MM_GEM0_SIZE 0x10000
118 #define MM_GEM1 0xff0d0000U
119 #define MM_GEM1_SIZE 0x10000
120
121 #define MM_ADMA_CH0 0xffa80000U
122 #define MM_ADMA_CH0_SIZE 0x10000
123
124 #define MM_OCM 0xfffc0000U
125 #define MM_OCM_SIZE 0x40000
126
127 #define MM_TOP_DDR 0x0
128 #define MM_TOP_DDR_SIZE 0x80000000U
129 #define MM_TOP_DDR_2 0x800000000ULL
130 #define MM_TOP_DDR_2_SIZE 0x800000000ULL
131 #define MM_TOP_DDR_3 0xc000000000ULL
132 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL
133 #define MM_TOP_DDR_4 0x10000000000ULL
134 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL
135
136 #define MM_PSM_START 0xffc80000U
137 #define MM_PSM_END 0xffcf0000U
138
139 #define MM_CRL 0xff5e0000U
140 #define MM_CRL_SIZE 0x300000
141 #define MM_IOU_SCNTR 0xff130000U
142 #define MM_IOU_SCNTR_SIZE 0x10000
143 #define MM_IOU_SCNTRS 0xff140000U
144 #define MM_IOU_SCNTRS_SIZE 0x10000
145 #define MM_FPD_CRF 0xfd1a0000U
146 #define MM_FPD_CRF_SIZE 0x140000
147
148 #define MM_PMC_SD0 0xf1040000U
149 #define MM_PMC_SD0_SIZE 0x10000
150 #define MM_PMC_CRP 0xf1260000U
151 #define MM_PMC_CRP_SIZE 0x10000
152 #define MM_PMC_RTC 0xf12a0000
153 #define MM_PMC_RTC_SIZE 0x10000
154 #endif