hw/arm/virt-acpi-build: name GIC CPU Interface Structure appropriately
[qemu.git] / include / hw / arm / xlnx-zynqmp.h
1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #ifndef XLNX_ZYNQMP_H
19
20 #include "qemu-common.h"
21 #include "hw/arm/arm.h"
22 #include "hw/intc/arm_gic.h"
23 #include "hw/net/cadence_gem.h"
24 #include "hw/char/cadence_uart.h"
25 #include "hw/ide/pci.h"
26 #include "hw/ide/ahci.h"
27 #include "hw/sd/sdhci.h"
28 #include "hw/ssi/xilinx_spips.h"
29 #include "hw/dma/xlnx_dpdma.h"
30 #include "hw/display/xlnx_dp.h"
31
32 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
33 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
34 TYPE_XLNX_ZYNQMP)
35
36 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
37 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
38 #define XLNX_ZYNQMP_NUM_GEMS 4
39 #define XLNX_ZYNQMP_NUM_UARTS 2
40 #define XLNX_ZYNQMP_NUM_SDHCI 2
41 #define XLNX_ZYNQMP_NUM_SPIS 2
42
43 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
44 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
45 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
46
47 #define XLNX_ZYNQMP_GIC_REGIONS 2
48
49 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
50 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
51 * aligned address in the 64k region. To implement each GIC region needs a
52 * number of memory region aliases.
53 */
54
55 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
56 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
57
58 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
59
60 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
61 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
62
63 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
64 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
65
66 typedef struct XlnxZynqMPState {
67 /*< private >*/
68 DeviceState parent_obj;
69
70 /*< public >*/
71 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
72 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
73 GICState gic;
74 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
75
76 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
77
78 MemoryRegion *ddr_ram;
79 MemoryRegion ddr_ram_low, ddr_ram_high;
80
81 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
82 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
83 SysbusAHCIState sata;
84 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
85 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
86 XlnxDPState dp;
87 XlnxDPDMAState dpdma;
88
89 char *boot_cpu;
90 ARMCPU *boot_cpu_ptr;
91
92 /* Has the ARM Security extensions? */
93 bool secure;
94 /* Has the RPU subsystem? */
95 bool has_rpu;
96 } XlnxZynqMPState;
97
98 #define XLNX_ZYNQMP_H
99 #endif