Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request...
[qemu.git] / include / hw / core / cpu.h
1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/hwaddr.h"
26 #include "exec/memattrs.h"
27 #include "qapi/qapi-types-run-state.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/rcu_queue.h"
30 #include "qemu/queue.h"
31 #include "qemu/thread.h"
32 #include "qemu/plugin.h"
33
34 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
35 void *opaque);
36
37 /**
38 * vaddr:
39 * Type wide enough to contain any #target_ulong virtual address.
40 */
41 typedef uint64_t vaddr;
42 #define VADDR_PRId PRId64
43 #define VADDR_PRIu PRIu64
44 #define VADDR_PRIo PRIo64
45 #define VADDR_PRIx PRIx64
46 #define VADDR_PRIX PRIX64
47 #define VADDR_MAX UINT64_MAX
48
49 /**
50 * SECTION:cpu
51 * @section_id: QEMU-cpu
52 * @title: CPU Class
53 * @short_description: Base class for all CPUs
54 */
55
56 #define TYPE_CPU "cpu"
57
58 /* Since this macro is used a lot in hot code paths and in conjunction with
59 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
60 * an unchecked cast.
61 */
62 #define CPU(obj) ((CPUState *)(obj))
63
64 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
65 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
66
67 typedef enum MMUAccessType {
68 MMU_DATA_LOAD = 0,
69 MMU_DATA_STORE = 1,
70 MMU_INST_FETCH = 2
71 } MMUAccessType;
72
73 typedef struct CPUWatchpoint CPUWatchpoint;
74
75 struct TranslationBlock;
76
77 /**
78 * CPUClass:
79 * @class_by_name: Callback to map -cpu command line model name to an
80 * instantiatable CPU type.
81 * @parse_features: Callback to parse command line arguments.
82 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
83 * @has_work: Callback for checking if there is work to do.
84 * @do_interrupt: Callback for interrupt handling.
85 * @do_unaligned_access: Callback for unaligned access handling, if
86 * the target defines #TARGET_ALIGNED_ONLY.
87 * @do_transaction_failed: Callback for handling failed memory transactions
88 * (ie bus faults or external aborts; not MMU faults)
89 * @virtio_is_big_endian: Callback to return %true if a CPU which supports
90 * runtime configurable endianness is currently big-endian. Non-configurable
91 * CPUs can use the default implementation of this method. This method should
92 * not be used by any callers other than the pre-1.0 virtio devices.
93 * @memory_rw_debug: Callback for GDB memory access.
94 * @dump_state: Callback for dumping state.
95 * @dump_statistics: Callback for dumping statistics.
96 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
97 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
98 * @get_memory_mapping: Callback for obtaining the memory mappings.
99 * @set_pc: Callback for setting the Program Counter register. This
100 * should have the semantics used by the target architecture when
101 * setting the PC from a source such as an ELF file entry point;
102 * for example on Arm it will also set the Thumb mode bit based
103 * on the least significant bit of the new PC value.
104 * If the target behaviour here is anything other than "set
105 * the PC register to the value passed in" then the target must
106 * also implement the synchronize_from_tb hook.
107 * @synchronize_from_tb: Callback for synchronizing state from a TCG
108 * #TranslationBlock. This is called when we abandon execution
109 * of a TB before starting it, and must set all parts of the CPU
110 * state which the previous TB in the chain may not have updated.
111 * This always includes at least the program counter; some targets
112 * will need to do more. If this hook is not implemented then the
113 * default is to call @set_pc(tb->pc).
114 * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
115 * address fault. For system mode, if the access is valid, call
116 * tlb_set_page and return true; if the access is invalid, and
117 * probe is true, return false; otherwise raise an exception and
118 * do not return. For user-only mode, always raise an exception
119 * and do not return.
120 * @get_phys_page_debug: Callback for obtaining a physical address.
121 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
122 * associated memory transaction attributes to use for the access.
123 * CPUs which use memory transaction attributes should implement this
124 * instead of get_phys_page_debug.
125 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
126 * a memory access with the specified memory transaction attributes.
127 * @gdb_read_register: Callback for letting GDB read a register.
128 * @gdb_write_register: Callback for letting GDB write a register.
129 * @debug_check_watchpoint: Callback: return true if the architectural
130 * watchpoint whose address has matched should really fire.
131 * @debug_excp_handler: Callback for handling debug exceptions.
132 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
133 * 64-bit VM coredump.
134 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
135 * note to a 32-bit VM coredump.
136 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
137 * 32-bit VM coredump.
138 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
139 * note to a 32-bit VM coredump.
140 * @vmsd: State description for migration.
141 * @gdb_num_core_regs: Number of core registers accessible to GDB.
142 * @gdb_core_xml_file: File name for core registers GDB XML description.
143 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
144 * before the insn which triggers a watchpoint rather than after it.
145 * @gdb_arch_name: Optional callback that returns the architecture name known
146 * to GDB. The caller must free the returned string with g_free.
147 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
148 * gdb stub. Returns a pointer to the XML contents for the specified XML file
149 * or NULL if the CPU doesn't have a dynamically generated content for it.
150 * @cpu_exec_enter: Callback for cpu_exec preparation.
151 * @cpu_exec_exit: Callback for cpu_exec cleanup.
152 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
153 * @disas_set_info: Setup architecture specific components of disassembly info
154 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
155 * address before attempting to match it against watchpoints.
156 *
157 * Represents a CPU family or model.
158 */
159 typedef struct CPUClass {
160 /*< private >*/
161 DeviceClass parent_class;
162 /*< public >*/
163
164 ObjectClass *(*class_by_name)(const char *cpu_model);
165 void (*parse_features)(const char *typename, char *str, Error **errp);
166
167 int reset_dump_flags;
168 bool (*has_work)(CPUState *cpu);
169 void (*do_interrupt)(CPUState *cpu);
170 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
171 MMUAccessType access_type,
172 int mmu_idx, uintptr_t retaddr);
173 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
174 unsigned size, MMUAccessType access_type,
175 int mmu_idx, MemTxAttrs attrs,
176 MemTxResult response, uintptr_t retaddr);
177 bool (*virtio_is_big_endian)(CPUState *cpu);
178 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
179 uint8_t *buf, int len, bool is_write);
180 void (*dump_state)(CPUState *cpu, FILE *, int flags);
181 GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
182 void (*dump_statistics)(CPUState *cpu, int flags);
183 int64_t (*get_arch_id)(CPUState *cpu);
184 bool (*get_paging_enabled)(const CPUState *cpu);
185 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
186 Error **errp);
187 void (*set_pc)(CPUState *cpu, vaddr value);
188 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
189 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
190 MMUAccessType access_type, int mmu_idx,
191 bool probe, uintptr_t retaddr);
192 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
193 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
194 MemTxAttrs *attrs);
195 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
196 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
197 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
198 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
199 void (*debug_excp_handler)(CPUState *cpu);
200
201 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
202 int cpuid, void *opaque);
203 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
204 void *opaque);
205 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
206 int cpuid, void *opaque);
207 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
208 void *opaque);
209
210 const VMStateDescription *vmsd;
211 const char *gdb_core_xml_file;
212 gchar * (*gdb_arch_name)(CPUState *cpu);
213 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
214 void (*cpu_exec_enter)(CPUState *cpu);
215 void (*cpu_exec_exit)(CPUState *cpu);
216 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
217
218 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
219 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
220 void (*tcg_initialize)(void);
221
222 /* Keep non-pointer data at the end to minimize holes. */
223 int gdb_num_core_regs;
224 bool gdb_stop_before_watchpoint;
225 } CPUClass;
226
227 /*
228 * Low 16 bits: number of cycles left, used only in icount mode.
229 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
230 * for this CPU and return to its top level loop (even in non-icount mode).
231 * This allows a single read-compare-cbranch-write sequence to test
232 * for both decrementer underflow and exceptions.
233 */
234 typedef union IcountDecr {
235 uint32_t u32;
236 struct {
237 #ifdef HOST_WORDS_BIGENDIAN
238 uint16_t high;
239 uint16_t low;
240 #else
241 uint16_t low;
242 uint16_t high;
243 #endif
244 } u16;
245 } IcountDecr;
246
247 typedef struct CPUBreakpoint {
248 vaddr pc;
249 int flags; /* BP_* */
250 QTAILQ_ENTRY(CPUBreakpoint) entry;
251 } CPUBreakpoint;
252
253 struct CPUWatchpoint {
254 vaddr vaddr;
255 vaddr len;
256 vaddr hitaddr;
257 MemTxAttrs hitattrs;
258 int flags; /* BP_* */
259 QTAILQ_ENTRY(CPUWatchpoint) entry;
260 };
261
262 struct KVMState;
263 struct kvm_run;
264
265 struct hax_vcpu_state;
266
267 #define TB_JMP_CACHE_BITS 12
268 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
269
270 /* work queue */
271
272 /* The union type allows passing of 64 bit target pointers on 32 bit
273 * hosts in a single parameter
274 */
275 typedef union {
276 int host_int;
277 unsigned long host_ulong;
278 void *host_ptr;
279 vaddr target_ptr;
280 } run_on_cpu_data;
281
282 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
283 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
284 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
285 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
286 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
287
288 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
289
290 struct qemu_work_item;
291
292 #define CPU_UNSET_NUMA_NODE_ID -1
293 #define CPU_TRACE_DSTATE_MAX_EVENTS 32
294
295 /**
296 * CPUState:
297 * @cpu_index: CPU index (informative).
298 * @cluster_index: Identifies which cluster this CPU is in.
299 * For boards which don't define clusters or for "loose" CPUs not assigned
300 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
301 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
302 * QOM parent.
303 * @nr_cores: Number of cores within this CPU package.
304 * @nr_threads: Number of threads within this CPU.
305 * @running: #true if CPU is currently running (lockless).
306 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
307 * valid under cpu_list_lock.
308 * @created: Indicates whether the CPU thread has been successfully created.
309 * @interrupt_request: Indicates a pending interrupt request.
310 * @halted: Nonzero if the CPU is in suspended state.
311 * @stop: Indicates a pending stop request.
312 * @stopped: Indicates the CPU has been artificially stopped.
313 * @unplug: Indicates a pending CPU unplug request.
314 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
315 * @singlestep_enabled: Flags for single-stepping.
316 * @icount_extra: Instructions until next timer event.
317 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
318 * requires that IO only be performed on the last instruction of a TB
319 * so that interrupts take effect immediately.
320 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
321 * AddressSpaces this CPU has)
322 * @num_ases: number of CPUAddressSpaces in @cpu_ases
323 * @as: Pointer to the first AddressSpace, for the convenience of targets which
324 * only have a single AddressSpace
325 * @env_ptr: Pointer to subclass-specific CPUArchState field.
326 * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
327 * @gdb_regs: Additional GDB registers.
328 * @gdb_num_regs: Number of total registers accessible to GDB.
329 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
330 * @next_cpu: Next CPU sharing TB cache.
331 * @opaque: User data.
332 * @mem_io_pc: Host Program Counter at which the memory was accessed.
333 * @kvm_fd: vCPU file descriptor for KVM.
334 * @work_mutex: Lock to prevent multiple access to queued_work_*.
335 * @queued_work_first: First asynchronous work pending.
336 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
337 * to @trace_dstate).
338 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
339 * @plugin_mask: Plugin event bitmap. Modified only via async work.
340 * @ignore_memory_transaction_failures: Cached copy of the MachineState
341 * flag of the same name: allows the board to suppress calling of the
342 * CPU do_transaction_failed hook function.
343 *
344 * State of one CPU core or thread.
345 */
346 struct CPUState {
347 /*< private >*/
348 DeviceState parent_obj;
349 /*< public >*/
350
351 int nr_cores;
352 int nr_threads;
353
354 struct QemuThread *thread;
355 #ifdef _WIN32
356 HANDLE hThread;
357 #endif
358 int thread_id;
359 bool running, has_waiter;
360 struct QemuCond *halt_cond;
361 bool thread_kicked;
362 bool created;
363 bool stop;
364 bool stopped;
365 bool unplug;
366 bool crash_occurred;
367 bool exit_request;
368 bool in_exclusive_context;
369 uint32_t cflags_next_tb;
370 /* updates protected by BQL */
371 uint32_t interrupt_request;
372 int singlestep_enabled;
373 int64_t icount_budget;
374 int64_t icount_extra;
375 uint64_t random_seed;
376 sigjmp_buf jmp_env;
377
378 QemuMutex work_mutex;
379 struct qemu_work_item *queued_work_first, *queued_work_last;
380
381 CPUAddressSpace *cpu_ases;
382 int num_ases;
383 AddressSpace *as;
384 MemoryRegion *memory;
385
386 void *env_ptr; /* CPUArchState */
387 IcountDecr *icount_decr_ptr;
388
389 /* Accessed in parallel; all accesses must be atomic */
390 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
391
392 struct GDBRegisterState *gdb_regs;
393 int gdb_num_regs;
394 int gdb_num_g_regs;
395 QTAILQ_ENTRY(CPUState) node;
396
397 /* ice debug support */
398 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
399
400 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
401 CPUWatchpoint *watchpoint_hit;
402
403 void *opaque;
404
405 /* In order to avoid passing too many arguments to the MMIO helpers,
406 * we store some rarely used information in the CPU context.
407 */
408 uintptr_t mem_io_pc;
409
410 int kvm_fd;
411 struct KVMState *kvm_state;
412 struct kvm_run *kvm_run;
413
414 /* Used for events with 'vcpu' and *without* the 'disabled' properties */
415 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS);
416 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS);
417
418 DECLARE_BITMAP(plugin_mask, QEMU_PLUGIN_EV_MAX);
419
420 GArray *plugin_mem_cbs;
421
422 /* TODO Move common fields from CPUArchState here. */
423 int cpu_index;
424 int cluster_index;
425 uint32_t halted;
426 uint32_t can_do_io;
427 int32_t exception_index;
428
429 /* shared by kvm, hax and hvf */
430 bool vcpu_dirty;
431
432 /* Used to keep track of an outstanding cpu throttle thread for migration
433 * autoconverge
434 */
435 bool throttle_thread_scheduled;
436
437 bool ignore_memory_transaction_failures;
438
439 struct hax_vcpu_state *hax_vcpu;
440
441 int hvf_fd;
442
443 /* track IOMMUs whose translations we've cached in the TCG TLB */
444 GArray *iommu_notifiers;
445 };
446
447 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
448 extern CPUTailQ cpus;
449
450 #define first_cpu QTAILQ_FIRST_RCU(&cpus)
451 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
452 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
453 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
454 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
455
456 extern __thread CPUState *current_cpu;
457
458 static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
459 {
460 unsigned int i;
461
462 for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
463 atomic_set(&cpu->tb_jmp_cache[i], NULL);
464 }
465 }
466
467 /**
468 * qemu_tcg_mttcg_enabled:
469 * Check whether we are running MultiThread TCG or not.
470 *
471 * Returns: %true if we are in MTTCG mode %false otherwise.
472 */
473 extern bool mttcg_enabled;
474 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
475
476 /**
477 * cpu_paging_enabled:
478 * @cpu: The CPU whose state is to be inspected.
479 *
480 * Returns: %true if paging is enabled, %false otherwise.
481 */
482 bool cpu_paging_enabled(const CPUState *cpu);
483
484 /**
485 * cpu_get_memory_mapping:
486 * @cpu: The CPU whose memory mappings are to be obtained.
487 * @list: Where to write the memory mappings to.
488 * @errp: Pointer for reporting an #Error.
489 */
490 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
491 Error **errp);
492
493 /**
494 * cpu_write_elf64_note:
495 * @f: pointer to a function that writes memory to a file
496 * @cpu: The CPU whose memory is to be dumped
497 * @cpuid: ID number of the CPU
498 * @opaque: pointer to the CPUState struct
499 */
500 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
501 int cpuid, void *opaque);
502
503 /**
504 * cpu_write_elf64_qemunote:
505 * @f: pointer to a function that writes memory to a file
506 * @cpu: The CPU whose memory is to be dumped
507 * @cpuid: ID number of the CPU
508 * @opaque: pointer to the CPUState struct
509 */
510 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
511 void *opaque);
512
513 /**
514 * cpu_write_elf32_note:
515 * @f: pointer to a function that writes memory to a file
516 * @cpu: The CPU whose memory is to be dumped
517 * @cpuid: ID number of the CPU
518 * @opaque: pointer to the CPUState struct
519 */
520 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
521 int cpuid, void *opaque);
522
523 /**
524 * cpu_write_elf32_qemunote:
525 * @f: pointer to a function that writes memory to a file
526 * @cpu: The CPU whose memory is to be dumped
527 * @cpuid: ID number of the CPU
528 * @opaque: pointer to the CPUState struct
529 */
530 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
531 void *opaque);
532
533 /**
534 * cpu_get_crash_info:
535 * @cpu: The CPU to get crash information for
536 *
537 * Gets the previously saved crash information.
538 * Caller is responsible for freeing the data.
539 */
540 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
541
542 /**
543 * CPUDumpFlags:
544 * @CPU_DUMP_CODE:
545 * @CPU_DUMP_FPU: dump FPU register state, not just integer
546 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
547 */
548 enum CPUDumpFlags {
549 CPU_DUMP_CODE = 0x00010000,
550 CPU_DUMP_FPU = 0x00020000,
551 CPU_DUMP_CCOP = 0x00040000,
552 };
553
554 /**
555 * cpu_dump_state:
556 * @cpu: The CPU whose state is to be dumped.
557 * @f: If non-null, dump to this stream, else to current print sink.
558 *
559 * Dumps CPU state.
560 */
561 void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
562
563 /**
564 * cpu_dump_statistics:
565 * @cpu: The CPU whose state is to be dumped.
566 * @flags: Flags what to dump.
567 *
568 * Dump CPU statistics to the current monitor if we have one, else to
569 * stdout.
570 */
571 void cpu_dump_statistics(CPUState *cpu, int flags);
572
573 #ifndef CONFIG_USER_ONLY
574 /**
575 * cpu_get_phys_page_attrs_debug:
576 * @cpu: The CPU to obtain the physical page address for.
577 * @addr: The virtual address.
578 * @attrs: Updated on return with the memory transaction attributes to use
579 * for this access.
580 *
581 * Obtains the physical page corresponding to a virtual one, together
582 * with the corresponding memory transaction attributes to use for the access.
583 * Use it only for debugging because no protection checks are done.
584 *
585 * Returns: Corresponding physical page address or -1 if no page found.
586 */
587 static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
588 MemTxAttrs *attrs)
589 {
590 CPUClass *cc = CPU_GET_CLASS(cpu);
591
592 if (cc->get_phys_page_attrs_debug) {
593 return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
594 }
595 /* Fallback for CPUs which don't implement the _attrs_ hook */
596 *attrs = MEMTXATTRS_UNSPECIFIED;
597 return cc->get_phys_page_debug(cpu, addr);
598 }
599
600 /**
601 * cpu_get_phys_page_debug:
602 * @cpu: The CPU to obtain the physical page address for.
603 * @addr: The virtual address.
604 *
605 * Obtains the physical page corresponding to a virtual one.
606 * Use it only for debugging because no protection checks are done.
607 *
608 * Returns: Corresponding physical page address or -1 if no page found.
609 */
610 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
611 {
612 MemTxAttrs attrs = {};
613
614 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
615 }
616
617 /** cpu_asidx_from_attrs:
618 * @cpu: CPU
619 * @attrs: memory transaction attributes
620 *
621 * Returns the address space index specifying the CPU AddressSpace
622 * to use for a memory access with the given transaction attributes.
623 */
624 static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
625 {
626 CPUClass *cc = CPU_GET_CLASS(cpu);
627 int ret = 0;
628
629 if (cc->asidx_from_attrs) {
630 ret = cc->asidx_from_attrs(cpu, attrs);
631 assert(ret < cpu->num_ases && ret >= 0);
632 }
633 return ret;
634 }
635 #endif
636
637 /**
638 * cpu_list_add:
639 * @cpu: The CPU to be added to the list of CPUs.
640 */
641 void cpu_list_add(CPUState *cpu);
642
643 /**
644 * cpu_list_remove:
645 * @cpu: The CPU to be removed from the list of CPUs.
646 */
647 void cpu_list_remove(CPUState *cpu);
648
649 /**
650 * cpu_reset:
651 * @cpu: The CPU whose state is to be reset.
652 */
653 void cpu_reset(CPUState *cpu);
654
655 /**
656 * cpu_class_by_name:
657 * @typename: The CPU base type.
658 * @cpu_model: The model string without any parameters.
659 *
660 * Looks up a CPU #ObjectClass matching name @cpu_model.
661 *
662 * Returns: A #CPUClass or %NULL if not matching class is found.
663 */
664 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
665
666 /**
667 * cpu_create:
668 * @typename: The CPU type.
669 *
670 * Instantiates a CPU and realizes the CPU.
671 *
672 * Returns: A #CPUState or %NULL if an error occurred.
673 */
674 CPUState *cpu_create(const char *typename);
675
676 /**
677 * parse_cpu_option:
678 * @cpu_option: The -cpu option including optional parameters.
679 *
680 * processes optional parameters and registers them as global properties
681 *
682 * Returns: type of CPU to create or prints error and terminates process
683 * if an error occurred.
684 */
685 const char *parse_cpu_option(const char *cpu_option);
686
687 /**
688 * cpu_has_work:
689 * @cpu: The vCPU to check.
690 *
691 * Checks whether the CPU has work to do.
692 *
693 * Returns: %true if the CPU has work, %false otherwise.
694 */
695 static inline bool cpu_has_work(CPUState *cpu)
696 {
697 CPUClass *cc = CPU_GET_CLASS(cpu);
698
699 g_assert(cc->has_work);
700 return cc->has_work(cpu);
701 }
702
703 /**
704 * qemu_cpu_is_self:
705 * @cpu: The vCPU to check against.
706 *
707 * Checks whether the caller is executing on the vCPU thread.
708 *
709 * Returns: %true if called from @cpu's thread, %false otherwise.
710 */
711 bool qemu_cpu_is_self(CPUState *cpu);
712
713 /**
714 * qemu_cpu_kick:
715 * @cpu: The vCPU to kick.
716 *
717 * Kicks @cpu's thread.
718 */
719 void qemu_cpu_kick(CPUState *cpu);
720
721 /**
722 * cpu_is_stopped:
723 * @cpu: The CPU to check.
724 *
725 * Checks whether the CPU is stopped.
726 *
727 * Returns: %true if run state is not running or if artificially stopped;
728 * %false otherwise.
729 */
730 bool cpu_is_stopped(CPUState *cpu);
731
732 /**
733 * do_run_on_cpu:
734 * @cpu: The vCPU to run on.
735 * @func: The function to be executed.
736 * @data: Data to pass to the function.
737 * @mutex: Mutex to release while waiting for @func to run.
738 *
739 * Used internally in the implementation of run_on_cpu.
740 */
741 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
742 QemuMutex *mutex);
743
744 /**
745 * run_on_cpu:
746 * @cpu: The vCPU to run on.
747 * @func: The function to be executed.
748 * @data: Data to pass to the function.
749 *
750 * Schedules the function @func for execution on the vCPU @cpu.
751 */
752 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
753
754 /**
755 * async_run_on_cpu:
756 * @cpu: The vCPU to run on.
757 * @func: The function to be executed.
758 * @data: Data to pass to the function.
759 *
760 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
761 */
762 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
763
764 /**
765 * async_safe_run_on_cpu:
766 * @cpu: The vCPU to run on.
767 * @func: The function to be executed.
768 * @data: Data to pass to the function.
769 *
770 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
771 * while all other vCPUs are sleeping.
772 *
773 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
774 * BQL.
775 */
776 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
777
778 /**
779 * cpu_in_exclusive_context()
780 * @cpu: The vCPU to check
781 *
782 * Returns true if @cpu is an exclusive context, for example running
783 * something which has previously been queued via async_safe_run_on_cpu().
784 */
785 static inline bool cpu_in_exclusive_context(const CPUState *cpu)
786 {
787 return cpu->in_exclusive_context;
788 }
789
790 /**
791 * qemu_get_cpu:
792 * @index: The CPUState@cpu_index value of the CPU to obtain.
793 *
794 * Gets a CPU matching @index.
795 *
796 * Returns: The CPU or %NULL if there is no matching CPU.
797 */
798 CPUState *qemu_get_cpu(int index);
799
800 /**
801 * cpu_exists:
802 * @id: Guest-exposed CPU ID to lookup.
803 *
804 * Search for CPU with specified ID.
805 *
806 * Returns: %true - CPU is found, %false - CPU isn't found.
807 */
808 bool cpu_exists(int64_t id);
809
810 /**
811 * cpu_by_arch_id:
812 * @id: Guest-exposed CPU ID of the CPU to obtain.
813 *
814 * Get a CPU with matching @id.
815 *
816 * Returns: The CPU or %NULL if there is no matching CPU.
817 */
818 CPUState *cpu_by_arch_id(int64_t id);
819
820 /**
821 * cpu_throttle_set:
822 * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
823 *
824 * Throttles all vcpus by forcing them to sleep for the given percentage of
825 * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
826 * (example: 10ms sleep for every 30ms awake).
827 *
828 * cpu_throttle_set can be called as needed to adjust new_throttle_pct.
829 * Once the throttling starts, it will remain in effect until cpu_throttle_stop
830 * is called.
831 */
832 void cpu_throttle_set(int new_throttle_pct);
833
834 /**
835 * cpu_throttle_stop:
836 *
837 * Stops the vcpu throttling started by cpu_throttle_set.
838 */
839 void cpu_throttle_stop(void);
840
841 /**
842 * cpu_throttle_active:
843 *
844 * Returns: %true if the vcpus are currently being throttled, %false otherwise.
845 */
846 bool cpu_throttle_active(void);
847
848 /**
849 * cpu_throttle_get_percentage:
850 *
851 * Returns the vcpu throttle percentage. See cpu_throttle_set for details.
852 *
853 * Returns: The throttle percentage in range 1 to 99.
854 */
855 int cpu_throttle_get_percentage(void);
856
857 #ifndef CONFIG_USER_ONLY
858
859 typedef void (*CPUInterruptHandler)(CPUState *, int);
860
861 extern CPUInterruptHandler cpu_interrupt_handler;
862
863 /**
864 * cpu_interrupt:
865 * @cpu: The CPU to set an interrupt on.
866 * @mask: The interrupts to set.
867 *
868 * Invokes the interrupt handler.
869 */
870 static inline void cpu_interrupt(CPUState *cpu, int mask)
871 {
872 cpu_interrupt_handler(cpu, mask);
873 }
874
875 #else /* USER_ONLY */
876
877 void cpu_interrupt(CPUState *cpu, int mask);
878
879 #endif /* USER_ONLY */
880
881 #ifdef NEED_CPU_H
882
883 #ifdef CONFIG_SOFTMMU
884 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
885 MMUAccessType access_type,
886 int mmu_idx, uintptr_t retaddr)
887 {
888 CPUClass *cc = CPU_GET_CLASS(cpu);
889
890 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
891 }
892
893 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
894 vaddr addr, unsigned size,
895 MMUAccessType access_type,
896 int mmu_idx, MemTxAttrs attrs,
897 MemTxResult response,
898 uintptr_t retaddr)
899 {
900 CPUClass *cc = CPU_GET_CLASS(cpu);
901
902 if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
903 cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
904 mmu_idx, attrs, response, retaddr);
905 }
906 }
907 #endif
908
909 #endif /* NEED_CPU_H */
910
911 /**
912 * cpu_set_pc:
913 * @cpu: The CPU to set the program counter for.
914 * @addr: Program counter value.
915 *
916 * Sets the program counter for a CPU.
917 */
918 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
919 {
920 CPUClass *cc = CPU_GET_CLASS(cpu);
921
922 cc->set_pc(cpu, addr);
923 }
924
925 /**
926 * cpu_reset_interrupt:
927 * @cpu: The CPU to clear the interrupt on.
928 * @mask: The interrupt mask to clear.
929 *
930 * Resets interrupts on the vCPU @cpu.
931 */
932 void cpu_reset_interrupt(CPUState *cpu, int mask);
933
934 /**
935 * cpu_exit:
936 * @cpu: The CPU to exit.
937 *
938 * Requests the CPU @cpu to exit execution.
939 */
940 void cpu_exit(CPUState *cpu);
941
942 /**
943 * cpu_resume:
944 * @cpu: The CPU to resume.
945 *
946 * Resumes CPU, i.e. puts CPU into runnable state.
947 */
948 void cpu_resume(CPUState *cpu);
949
950 /**
951 * cpu_remove:
952 * @cpu: The CPU to remove.
953 *
954 * Requests the CPU to be removed.
955 */
956 void cpu_remove(CPUState *cpu);
957
958 /**
959 * cpu_remove_sync:
960 * @cpu: The CPU to remove.
961 *
962 * Requests the CPU to be removed and waits till it is removed.
963 */
964 void cpu_remove_sync(CPUState *cpu);
965
966 /**
967 * process_queued_cpu_work() - process all items on CPU work queue
968 * @cpu: The CPU which work queue to process.
969 */
970 void process_queued_cpu_work(CPUState *cpu);
971
972 /**
973 * cpu_exec_start:
974 * @cpu: The CPU for the current thread.
975 *
976 * Record that a CPU has started execution and can be interrupted with
977 * cpu_exit.
978 */
979 void cpu_exec_start(CPUState *cpu);
980
981 /**
982 * cpu_exec_end:
983 * @cpu: The CPU for the current thread.
984 *
985 * Record that a CPU has stopped execution and exclusive sections
986 * can be executed without interrupting it.
987 */
988 void cpu_exec_end(CPUState *cpu);
989
990 /**
991 * start_exclusive:
992 *
993 * Wait for a concurrent exclusive section to end, and then start
994 * a section of work that is run while other CPUs are not running
995 * between cpu_exec_start and cpu_exec_end. CPUs that are running
996 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
997 * during the exclusive section go to sleep until this CPU calls
998 * end_exclusive.
999 */
1000 void start_exclusive(void);
1001
1002 /**
1003 * end_exclusive:
1004 *
1005 * Concludes an exclusive execution section started by start_exclusive.
1006 */
1007 void end_exclusive(void);
1008
1009 /**
1010 * qemu_init_vcpu:
1011 * @cpu: The vCPU to initialize.
1012 *
1013 * Initializes a vCPU.
1014 */
1015 void qemu_init_vcpu(CPUState *cpu);
1016
1017 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1018 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1019 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1020
1021 /**
1022 * cpu_single_step:
1023 * @cpu: CPU to the flags for.
1024 * @enabled: Flags to enable.
1025 *
1026 * Enables or disables single-stepping for @cpu.
1027 */
1028 void cpu_single_step(CPUState *cpu, int enabled);
1029
1030 /* Breakpoint/watchpoint flags */
1031 #define BP_MEM_READ 0x01
1032 #define BP_MEM_WRITE 0x02
1033 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1034 #define BP_STOP_BEFORE_ACCESS 0x04
1035 /* 0x08 currently unused */
1036 #define BP_GDB 0x10
1037 #define BP_CPU 0x20
1038 #define BP_ANY (BP_GDB | BP_CPU)
1039 #define BP_WATCHPOINT_HIT_READ 0x40
1040 #define BP_WATCHPOINT_HIT_WRITE 0x80
1041 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
1042
1043 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1044 CPUBreakpoint **breakpoint);
1045 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
1046 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
1047 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
1048
1049 /* Return true if PC matches an installed breakpoint. */
1050 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
1051 {
1052 CPUBreakpoint *bp;
1053
1054 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
1055 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1056 if (bp->pc == pc && (bp->flags & mask)) {
1057 return true;
1058 }
1059 }
1060 }
1061 return false;
1062 }
1063
1064 #ifdef CONFIG_USER_ONLY
1065 static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1066 int flags, CPUWatchpoint **watchpoint)
1067 {
1068 return -ENOSYS;
1069 }
1070
1071 static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1072 vaddr len, int flags)
1073 {
1074 return -ENOSYS;
1075 }
1076
1077 static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu,
1078 CPUWatchpoint *wp)
1079 {
1080 }
1081
1082 static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
1083 {
1084 }
1085
1086 static inline void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
1087 MemTxAttrs atr, int fl, uintptr_t ra)
1088 {
1089 }
1090
1091 static inline int cpu_watchpoint_address_matches(CPUState *cpu,
1092 vaddr addr, vaddr len)
1093 {
1094 return 0;
1095 }
1096 #else
1097 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1098 int flags, CPUWatchpoint **watchpoint);
1099 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1100 vaddr len, int flags);
1101 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
1102 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
1103 void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
1104 MemTxAttrs attrs, int flags, uintptr_t ra);
1105 int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len);
1106 #endif
1107
1108 /**
1109 * cpu_get_address_space:
1110 * @cpu: CPU to get address space from
1111 * @asidx: index identifying which address space to get
1112 *
1113 * Return the requested address space of this CPU. @asidx
1114 * specifies which address space to read.
1115 */
1116 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1117
1118 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
1119 GCC_FMT_ATTR(2, 3);
1120 extern Property cpu_common_props[];
1121 void cpu_exec_initfn(CPUState *cpu);
1122 void cpu_exec_realizefn(CPUState *cpu, Error **errp);
1123 void cpu_exec_unrealizefn(CPUState *cpu);
1124
1125 /**
1126 * target_words_bigendian:
1127 * Returns true if the (default) endianness of the target is big endian,
1128 * false otherwise. Note that in target-specific code, you can use
1129 * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common
1130 * code should normally never need to know about the endianness of the
1131 * target, so please do *not* use this function unless you know very well
1132 * what you are doing!
1133 */
1134 bool target_words_bigendian(void);
1135
1136 #ifdef NEED_CPU_H
1137
1138 #ifdef CONFIG_SOFTMMU
1139 extern const VMStateDescription vmstate_cpu_common;
1140 #else
1141 #define vmstate_cpu_common vmstate_dummy
1142 #endif
1143
1144 #define VMSTATE_CPU() { \
1145 .name = "parent_obj", \
1146 .size = sizeof(CPUState), \
1147 .vmsd = &vmstate_cpu_common, \
1148 .flags = VMS_STRUCT, \
1149 .offset = 0, \
1150 }
1151
1152 #endif /* NEED_CPU_H */
1153
1154 #define UNASSIGNED_CPU_INDEX -1
1155 #define UNASSIGNED_CLUSTER_INDEX -1
1156
1157 #endif