Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' into staging
[qemu.git] / include / hw / core / cpu.h
1 /*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20 #ifndef QEMU_CPU_H
21 #define QEMU_CPU_H
22
23 #include "hw/qdev-core.h"
24 #include "disas/dis-asm.h"
25 #include "exec/hwaddr.h"
26 #include "exec/memattrs.h"
27 #include "qapi/qapi-types-run-state.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/rcu_queue.h"
30 #include "qemu/queue.h"
31 #include "qemu/thread.h"
32
33 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
34 void *opaque);
35
36 /**
37 * vaddr:
38 * Type wide enough to contain any #target_ulong virtual address.
39 */
40 typedef uint64_t vaddr;
41 #define VADDR_PRId PRId64
42 #define VADDR_PRIu PRIu64
43 #define VADDR_PRIo PRIo64
44 #define VADDR_PRIx PRIx64
45 #define VADDR_PRIX PRIX64
46 #define VADDR_MAX UINT64_MAX
47
48 /**
49 * SECTION:cpu
50 * @section_id: QEMU-cpu
51 * @title: CPU Class
52 * @short_description: Base class for all CPUs
53 */
54
55 #define TYPE_CPU "cpu"
56
57 /* Since this macro is used a lot in hot code paths and in conjunction with
58 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
59 * an unchecked cast.
60 */
61 #define CPU(obj) ((CPUState *)(obj))
62
63 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
64 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
65
66 typedef enum MMUAccessType {
67 MMU_DATA_LOAD = 0,
68 MMU_DATA_STORE = 1,
69 MMU_INST_FETCH = 2
70 } MMUAccessType;
71
72 typedef struct CPUWatchpoint CPUWatchpoint;
73
74 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
75 bool is_write, bool is_exec, int opaque,
76 unsigned size);
77
78 struct TranslationBlock;
79
80 /**
81 * CPUClass:
82 * @class_by_name: Callback to map -cpu command line model name to an
83 * instantiatable CPU type.
84 * @parse_features: Callback to parse command line arguments.
85 * @reset: Callback to reset the #CPUState to its initial state.
86 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
87 * @has_work: Callback for checking if there is work to do.
88 * @do_interrupt: Callback for interrupt handling.
89 * @do_unassigned_access: Callback for unassigned access handling.
90 * (this is deprecated: new targets should use do_transaction_failed instead)
91 * @do_unaligned_access: Callback for unaligned access handling, if
92 * the target defines #TARGET_ALIGNED_ONLY.
93 * @do_transaction_failed: Callback for handling failed memory transactions
94 * (ie bus faults or external aborts; not MMU faults)
95 * @virtio_is_big_endian: Callback to return %true if a CPU which supports
96 * runtime configurable endianness is currently big-endian. Non-configurable
97 * CPUs can use the default implementation of this method. This method should
98 * not be used by any callers other than the pre-1.0 virtio devices.
99 * @memory_rw_debug: Callback for GDB memory access.
100 * @dump_state: Callback for dumping state.
101 * @dump_statistics: Callback for dumping statistics.
102 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
103 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
104 * @get_memory_mapping: Callback for obtaining the memory mappings.
105 * @set_pc: Callback for setting the Program Counter register. This
106 * should have the semantics used by the target architecture when
107 * setting the PC from a source such as an ELF file entry point;
108 * for example on Arm it will also set the Thumb mode bit based
109 * on the least significant bit of the new PC value.
110 * If the target behaviour here is anything other than "set
111 * the PC register to the value passed in" then the target must
112 * also implement the synchronize_from_tb hook.
113 * @synchronize_from_tb: Callback for synchronizing state from a TCG
114 * #TranslationBlock. This is called when we abandon execution
115 * of a TB before starting it, and must set all parts of the CPU
116 * state which the previous TB in the chain may not have updated.
117 * This always includes at least the program counter; some targets
118 * will need to do more. If this hook is not implemented then the
119 * default is to call @set_pc(tb->pc).
120 * @tlb_fill: Callback for handling a softmmu tlb miss or user-only
121 * address fault. For system mode, if the access is valid, call
122 * tlb_set_page and return true; if the access is invalid, and
123 * probe is true, return false; otherwise raise an exception and
124 * do not return. For user-only mode, always raise an exception
125 * and do not return.
126 * @get_phys_page_debug: Callback for obtaining a physical address.
127 * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
128 * associated memory transaction attributes to use for the access.
129 * CPUs which use memory transaction attributes should implement this
130 * instead of get_phys_page_debug.
131 * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
132 * a memory access with the specified memory transaction attributes.
133 * @gdb_read_register: Callback for letting GDB read a register.
134 * @gdb_write_register: Callback for letting GDB write a register.
135 * @debug_check_watchpoint: Callback: return true if the architectural
136 * watchpoint whose address has matched should really fire.
137 * @debug_excp_handler: Callback for handling debug exceptions.
138 * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
139 * 64-bit VM coredump.
140 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
141 * note to a 32-bit VM coredump.
142 * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
143 * 32-bit VM coredump.
144 * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
145 * note to a 32-bit VM coredump.
146 * @vmsd: State description for migration.
147 * @gdb_num_core_regs: Number of core registers accessible to GDB.
148 * @gdb_core_xml_file: File name for core registers GDB XML description.
149 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
150 * before the insn which triggers a watchpoint rather than after it.
151 * @gdb_arch_name: Optional callback that returns the architecture name known
152 * to GDB. The caller must free the returned string with g_free.
153 * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for the
154 * gdb stub. Returns a pointer to the XML contents for the specified XML file
155 * or NULL if the CPU doesn't have a dynamically generated content for it.
156 * @cpu_exec_enter: Callback for cpu_exec preparation.
157 * @cpu_exec_exit: Callback for cpu_exec cleanup.
158 * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
159 * @disas_set_info: Setup architecture specific components of disassembly info
160 * @adjust_watchpoint_address: Perform a target-specific adjustment to an
161 * address before attempting to match it against watchpoints.
162 *
163 * Represents a CPU family or model.
164 */
165 typedef struct CPUClass {
166 /*< private >*/
167 DeviceClass parent_class;
168 /*< public >*/
169
170 ObjectClass *(*class_by_name)(const char *cpu_model);
171 void (*parse_features)(const char *typename, char *str, Error **errp);
172
173 void (*reset)(CPUState *cpu);
174 int reset_dump_flags;
175 bool (*has_work)(CPUState *cpu);
176 void (*do_interrupt)(CPUState *cpu);
177 CPUUnassignedAccess do_unassigned_access;
178 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
179 MMUAccessType access_type,
180 int mmu_idx, uintptr_t retaddr);
181 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
182 unsigned size, MMUAccessType access_type,
183 int mmu_idx, MemTxAttrs attrs,
184 MemTxResult response, uintptr_t retaddr);
185 bool (*virtio_is_big_endian)(CPUState *cpu);
186 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
187 uint8_t *buf, int len, bool is_write);
188 void (*dump_state)(CPUState *cpu, FILE *, int flags);
189 GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
190 void (*dump_statistics)(CPUState *cpu, int flags);
191 int64_t (*get_arch_id)(CPUState *cpu);
192 bool (*get_paging_enabled)(const CPUState *cpu);
193 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
194 Error **errp);
195 void (*set_pc)(CPUState *cpu, vaddr value);
196 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
197 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
198 MMUAccessType access_type, int mmu_idx,
199 bool probe, uintptr_t retaddr);
200 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
201 hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
202 MemTxAttrs *attrs);
203 int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
204 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
205 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
206 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
207 void (*debug_excp_handler)(CPUState *cpu);
208
209 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
210 int cpuid, void *opaque);
211 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
212 void *opaque);
213 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
214 int cpuid, void *opaque);
215 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
216 void *opaque);
217
218 const VMStateDescription *vmsd;
219 const char *gdb_core_xml_file;
220 gchar * (*gdb_arch_name)(CPUState *cpu);
221 const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
222 void (*cpu_exec_enter)(CPUState *cpu);
223 void (*cpu_exec_exit)(CPUState *cpu);
224 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
225
226 void (*disas_set_info)(CPUState *cpu, disassemble_info *info);
227 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
228 void (*tcg_initialize)(void);
229
230 /* Keep non-pointer data at the end to minimize holes. */
231 int gdb_num_core_regs;
232 bool gdb_stop_before_watchpoint;
233 } CPUClass;
234
235 /*
236 * Low 16 bits: number of cycles left, used only in icount mode.
237 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs
238 * for this CPU and return to its top level loop (even in non-icount mode).
239 * This allows a single read-compare-cbranch-write sequence to test
240 * for both decrementer underflow and exceptions.
241 */
242 typedef union IcountDecr {
243 uint32_t u32;
244 struct {
245 #ifdef HOST_WORDS_BIGENDIAN
246 uint16_t high;
247 uint16_t low;
248 #else
249 uint16_t low;
250 uint16_t high;
251 #endif
252 } u16;
253 } IcountDecr;
254
255 typedef struct CPUBreakpoint {
256 vaddr pc;
257 int flags; /* BP_* */
258 QTAILQ_ENTRY(CPUBreakpoint) entry;
259 } CPUBreakpoint;
260
261 struct CPUWatchpoint {
262 vaddr vaddr;
263 vaddr len;
264 vaddr hitaddr;
265 MemTxAttrs hitattrs;
266 int flags; /* BP_* */
267 QTAILQ_ENTRY(CPUWatchpoint) entry;
268 };
269
270 struct KVMState;
271 struct kvm_run;
272
273 struct hax_vcpu_state;
274
275 #define TB_JMP_CACHE_BITS 12
276 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
277
278 /* work queue */
279
280 /* The union type allows passing of 64 bit target pointers on 32 bit
281 * hosts in a single parameter
282 */
283 typedef union {
284 int host_int;
285 unsigned long host_ulong;
286 void *host_ptr;
287 vaddr target_ptr;
288 } run_on_cpu_data;
289
290 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)})
291 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)})
292 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)})
293 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)})
294 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL)
295
296 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data);
297
298 struct qemu_work_item;
299
300 #define CPU_UNSET_NUMA_NODE_ID -1
301 #define CPU_TRACE_DSTATE_MAX_EVENTS 32
302
303 /**
304 * CPUState:
305 * @cpu_index: CPU index (informative).
306 * @cluster_index: Identifies which cluster this CPU is in.
307 * For boards which don't define clusters or for "loose" CPUs not assigned
308 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will
309 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER
310 * QOM parent.
311 * @nr_cores: Number of cores within this CPU package.
312 * @nr_threads: Number of threads within this CPU.
313 * @running: #true if CPU is currently running (lockless).
314 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end;
315 * valid under cpu_list_lock.
316 * @created: Indicates whether the CPU thread has been successfully created.
317 * @interrupt_request: Indicates a pending interrupt request.
318 * @halted: Nonzero if the CPU is in suspended state.
319 * @stop: Indicates a pending stop request.
320 * @stopped: Indicates the CPU has been artificially stopped.
321 * @unplug: Indicates a pending CPU unplug request.
322 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU
323 * @singlestep_enabled: Flags for single-stepping.
324 * @icount_extra: Instructions until next timer event.
325 * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution
326 * requires that IO only be performed on the last instruction of a TB
327 * so that interrupts take effect immediately.
328 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the
329 * AddressSpaces this CPU has)
330 * @num_ases: number of CPUAddressSpaces in @cpu_ases
331 * @as: Pointer to the first AddressSpace, for the convenience of targets which
332 * only have a single AddressSpace
333 * @env_ptr: Pointer to subclass-specific CPUArchState field.
334 * @icount_decr_ptr: Pointer to IcountDecr field within subclass.
335 * @gdb_regs: Additional GDB registers.
336 * @gdb_num_regs: Number of total registers accessible to GDB.
337 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
338 * @next_cpu: Next CPU sharing TB cache.
339 * @opaque: User data.
340 * @mem_io_pc: Host Program Counter at which the memory was accessed.
341 * @mem_io_vaddr: Target virtual address at which the memory was accessed.
342 * @kvm_fd: vCPU file descriptor for KVM.
343 * @work_mutex: Lock to prevent multiple access to queued_work_*.
344 * @queued_work_first: First asynchronous work pending.
345 * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all changes
346 * to @trace_dstate).
347 * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask).
348 * @ignore_memory_transaction_failures: Cached copy of the MachineState
349 * flag of the same name: allows the board to suppress calling of the
350 * CPU do_transaction_failed hook function.
351 *
352 * State of one CPU core or thread.
353 */
354 struct CPUState {
355 /*< private >*/
356 DeviceState parent_obj;
357 /*< public >*/
358
359 int nr_cores;
360 int nr_threads;
361
362 struct QemuThread *thread;
363 #ifdef _WIN32
364 HANDLE hThread;
365 #endif
366 int thread_id;
367 bool running, has_waiter;
368 struct QemuCond *halt_cond;
369 bool thread_kicked;
370 bool created;
371 bool stop;
372 bool stopped;
373 bool unplug;
374 bool crash_occurred;
375 bool exit_request;
376 uint32_t cflags_next_tb;
377 /* updates protected by BQL */
378 uint32_t interrupt_request;
379 int singlestep_enabled;
380 int64_t icount_budget;
381 int64_t icount_extra;
382 uint64_t random_seed;
383 sigjmp_buf jmp_env;
384
385 QemuMutex work_mutex;
386 struct qemu_work_item *queued_work_first, *queued_work_last;
387
388 CPUAddressSpace *cpu_ases;
389 int num_ases;
390 AddressSpace *as;
391 MemoryRegion *memory;
392
393 void *env_ptr; /* CPUArchState */
394 IcountDecr *icount_decr_ptr;
395
396 /* Accessed in parallel; all accesses must be atomic */
397 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
398
399 struct GDBRegisterState *gdb_regs;
400 int gdb_num_regs;
401 int gdb_num_g_regs;
402 QTAILQ_ENTRY(CPUState) node;
403
404 /* ice debug support */
405 QTAILQ_HEAD(, CPUBreakpoint) breakpoints;
406
407 QTAILQ_HEAD(, CPUWatchpoint) watchpoints;
408 CPUWatchpoint *watchpoint_hit;
409
410 void *opaque;
411
412 /* In order to avoid passing too many arguments to the MMIO helpers,
413 * we store some rarely used information in the CPU context.
414 */
415 uintptr_t mem_io_pc;
416 vaddr mem_io_vaddr;
417 /*
418 * This is only needed for the legacy cpu_unassigned_access() hook;
419 * when all targets using it have been converted to use
420 * cpu_transaction_failed() instead it can be removed.
421 */
422 MMUAccessType mem_io_access_type;
423
424 int kvm_fd;
425 struct KVMState *kvm_state;
426 struct kvm_run *kvm_run;
427
428 /* Used for events with 'vcpu' and *without* the 'disabled' properties */
429 DECLARE_BITMAP(trace_dstate_delayed, CPU_TRACE_DSTATE_MAX_EVENTS);
430 DECLARE_BITMAP(trace_dstate, CPU_TRACE_DSTATE_MAX_EVENTS);
431
432 /* TODO Move common fields from CPUArchState here. */
433 int cpu_index;
434 int cluster_index;
435 uint32_t halted;
436 uint32_t can_do_io;
437 int32_t exception_index;
438
439 /* shared by kvm, hax and hvf */
440 bool vcpu_dirty;
441
442 /* Used to keep track of an outstanding cpu throttle thread for migration
443 * autoconverge
444 */
445 bool throttle_thread_scheduled;
446
447 bool ignore_memory_transaction_failures;
448
449 struct hax_vcpu_state *hax_vcpu;
450
451 int hvf_fd;
452
453 /* track IOMMUs whose translations we've cached in the TCG TLB */
454 GArray *iommu_notifiers;
455 };
456
457 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ;
458 extern CPUTailQ cpus;
459
460 #define first_cpu QTAILQ_FIRST_RCU(&cpus)
461 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node)
462 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus, node)
463 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
464 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus, node, next_cpu)
465
466 extern __thread CPUState *current_cpu;
467
468 static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
469 {
470 unsigned int i;
471
472 for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
473 atomic_set(&cpu->tb_jmp_cache[i], NULL);
474 }
475 }
476
477 /**
478 * qemu_tcg_mttcg_enabled:
479 * Check whether we are running MultiThread TCG or not.
480 *
481 * Returns: %true if we are in MTTCG mode %false otherwise.
482 */
483 extern bool mttcg_enabled;
484 #define qemu_tcg_mttcg_enabled() (mttcg_enabled)
485
486 /**
487 * cpu_paging_enabled:
488 * @cpu: The CPU whose state is to be inspected.
489 *
490 * Returns: %true if paging is enabled, %false otherwise.
491 */
492 bool cpu_paging_enabled(const CPUState *cpu);
493
494 /**
495 * cpu_get_memory_mapping:
496 * @cpu: The CPU whose memory mappings are to be obtained.
497 * @list: Where to write the memory mappings to.
498 * @errp: Pointer for reporting an #Error.
499 */
500 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
501 Error **errp);
502
503 /**
504 * cpu_write_elf64_note:
505 * @f: pointer to a function that writes memory to a file
506 * @cpu: The CPU whose memory is to be dumped
507 * @cpuid: ID number of the CPU
508 * @opaque: pointer to the CPUState struct
509 */
510 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
511 int cpuid, void *opaque);
512
513 /**
514 * cpu_write_elf64_qemunote:
515 * @f: pointer to a function that writes memory to a file
516 * @cpu: The CPU whose memory is to be dumped
517 * @cpuid: ID number of the CPU
518 * @opaque: pointer to the CPUState struct
519 */
520 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
521 void *opaque);
522
523 /**
524 * cpu_write_elf32_note:
525 * @f: pointer to a function that writes memory to a file
526 * @cpu: The CPU whose memory is to be dumped
527 * @cpuid: ID number of the CPU
528 * @opaque: pointer to the CPUState struct
529 */
530 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
531 int cpuid, void *opaque);
532
533 /**
534 * cpu_write_elf32_qemunote:
535 * @f: pointer to a function that writes memory to a file
536 * @cpu: The CPU whose memory is to be dumped
537 * @cpuid: ID number of the CPU
538 * @opaque: pointer to the CPUState struct
539 */
540 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
541 void *opaque);
542
543 /**
544 * cpu_get_crash_info:
545 * @cpu: The CPU to get crash information for
546 *
547 * Gets the previously saved crash information.
548 * Caller is responsible for freeing the data.
549 */
550 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
551
552 /**
553 * CPUDumpFlags:
554 * @CPU_DUMP_CODE:
555 * @CPU_DUMP_FPU: dump FPU register state, not just integer
556 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
557 */
558 enum CPUDumpFlags {
559 CPU_DUMP_CODE = 0x00010000,
560 CPU_DUMP_FPU = 0x00020000,
561 CPU_DUMP_CCOP = 0x00040000,
562 };
563
564 /**
565 * cpu_dump_state:
566 * @cpu: The CPU whose state is to be dumped.
567 * @f: If non-null, dump to this stream, else to current print sink.
568 *
569 * Dumps CPU state.
570 */
571 void cpu_dump_state(CPUState *cpu, FILE *f, int flags);
572
573 /**
574 * cpu_dump_statistics:
575 * @cpu: The CPU whose state is to be dumped.
576 * @flags: Flags what to dump.
577 *
578 * Dump CPU statistics to the current monitor if we have one, else to
579 * stdout.
580 */
581 void cpu_dump_statistics(CPUState *cpu, int flags);
582
583 #ifndef CONFIG_USER_ONLY
584 /**
585 * cpu_get_phys_page_attrs_debug:
586 * @cpu: The CPU to obtain the physical page address for.
587 * @addr: The virtual address.
588 * @attrs: Updated on return with the memory transaction attributes to use
589 * for this access.
590 *
591 * Obtains the physical page corresponding to a virtual one, together
592 * with the corresponding memory transaction attributes to use for the access.
593 * Use it only for debugging because no protection checks are done.
594 *
595 * Returns: Corresponding physical page address or -1 if no page found.
596 */
597 static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
598 MemTxAttrs *attrs)
599 {
600 CPUClass *cc = CPU_GET_CLASS(cpu);
601
602 if (cc->get_phys_page_attrs_debug) {
603 return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
604 }
605 /* Fallback for CPUs which don't implement the _attrs_ hook */
606 *attrs = MEMTXATTRS_UNSPECIFIED;
607 return cc->get_phys_page_debug(cpu, addr);
608 }
609
610 /**
611 * cpu_get_phys_page_debug:
612 * @cpu: The CPU to obtain the physical page address for.
613 * @addr: The virtual address.
614 *
615 * Obtains the physical page corresponding to a virtual one.
616 * Use it only for debugging because no protection checks are done.
617 *
618 * Returns: Corresponding physical page address or -1 if no page found.
619 */
620 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
621 {
622 MemTxAttrs attrs = {};
623
624 return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
625 }
626
627 /** cpu_asidx_from_attrs:
628 * @cpu: CPU
629 * @attrs: memory transaction attributes
630 *
631 * Returns the address space index specifying the CPU AddressSpace
632 * to use for a memory access with the given transaction attributes.
633 */
634 static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
635 {
636 CPUClass *cc = CPU_GET_CLASS(cpu);
637 int ret = 0;
638
639 if (cc->asidx_from_attrs) {
640 ret = cc->asidx_from_attrs(cpu, attrs);
641 assert(ret < cpu->num_ases && ret >= 0);
642 }
643 return ret;
644 }
645 #endif
646
647 /**
648 * cpu_list_add:
649 * @cpu: The CPU to be added to the list of CPUs.
650 */
651 void cpu_list_add(CPUState *cpu);
652
653 /**
654 * cpu_list_remove:
655 * @cpu: The CPU to be removed from the list of CPUs.
656 */
657 void cpu_list_remove(CPUState *cpu);
658
659 /**
660 * cpu_reset:
661 * @cpu: The CPU whose state is to be reset.
662 */
663 void cpu_reset(CPUState *cpu);
664
665 /**
666 * cpu_class_by_name:
667 * @typename: The CPU base type.
668 * @cpu_model: The model string without any parameters.
669 *
670 * Looks up a CPU #ObjectClass matching name @cpu_model.
671 *
672 * Returns: A #CPUClass or %NULL if not matching class is found.
673 */
674 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
675
676 /**
677 * cpu_create:
678 * @typename: The CPU type.
679 *
680 * Instantiates a CPU and realizes the CPU.
681 *
682 * Returns: A #CPUState or %NULL if an error occurred.
683 */
684 CPUState *cpu_create(const char *typename);
685
686 /**
687 * parse_cpu_option:
688 * @cpu_option: The -cpu option including optional parameters.
689 *
690 * processes optional parameters and registers them as global properties
691 *
692 * Returns: type of CPU to create or prints error and terminates process
693 * if an error occurred.
694 */
695 const char *parse_cpu_option(const char *cpu_option);
696
697 /**
698 * cpu_has_work:
699 * @cpu: The vCPU to check.
700 *
701 * Checks whether the CPU has work to do.
702 *
703 * Returns: %true if the CPU has work, %false otherwise.
704 */
705 static inline bool cpu_has_work(CPUState *cpu)
706 {
707 CPUClass *cc = CPU_GET_CLASS(cpu);
708
709 g_assert(cc->has_work);
710 return cc->has_work(cpu);
711 }
712
713 /**
714 * qemu_cpu_is_self:
715 * @cpu: The vCPU to check against.
716 *
717 * Checks whether the caller is executing on the vCPU thread.
718 *
719 * Returns: %true if called from @cpu's thread, %false otherwise.
720 */
721 bool qemu_cpu_is_self(CPUState *cpu);
722
723 /**
724 * qemu_cpu_kick:
725 * @cpu: The vCPU to kick.
726 *
727 * Kicks @cpu's thread.
728 */
729 void qemu_cpu_kick(CPUState *cpu);
730
731 /**
732 * cpu_is_stopped:
733 * @cpu: The CPU to check.
734 *
735 * Checks whether the CPU is stopped.
736 *
737 * Returns: %true if run state is not running or if artificially stopped;
738 * %false otherwise.
739 */
740 bool cpu_is_stopped(CPUState *cpu);
741
742 /**
743 * do_run_on_cpu:
744 * @cpu: The vCPU to run on.
745 * @func: The function to be executed.
746 * @data: Data to pass to the function.
747 * @mutex: Mutex to release while waiting for @func to run.
748 *
749 * Used internally in the implementation of run_on_cpu.
750 */
751 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data,
752 QemuMutex *mutex);
753
754 /**
755 * run_on_cpu:
756 * @cpu: The vCPU to run on.
757 * @func: The function to be executed.
758 * @data: Data to pass to the function.
759 *
760 * Schedules the function @func for execution on the vCPU @cpu.
761 */
762 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
763
764 /**
765 * async_run_on_cpu:
766 * @cpu: The vCPU to run on.
767 * @func: The function to be executed.
768 * @data: Data to pass to the function.
769 *
770 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
771 */
772 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
773
774 /**
775 * async_safe_run_on_cpu:
776 * @cpu: The vCPU to run on.
777 * @func: The function to be executed.
778 * @data: Data to pass to the function.
779 *
780 * Schedules the function @func for execution on the vCPU @cpu asynchronously,
781 * while all other vCPUs are sleeping.
782 *
783 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the
784 * BQL.
785 */
786 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data);
787
788 /**
789 * qemu_get_cpu:
790 * @index: The CPUState@cpu_index value of the CPU to obtain.
791 *
792 * Gets a CPU matching @index.
793 *
794 * Returns: The CPU or %NULL if there is no matching CPU.
795 */
796 CPUState *qemu_get_cpu(int index);
797
798 /**
799 * cpu_exists:
800 * @id: Guest-exposed CPU ID to lookup.
801 *
802 * Search for CPU with specified ID.
803 *
804 * Returns: %true - CPU is found, %false - CPU isn't found.
805 */
806 bool cpu_exists(int64_t id);
807
808 /**
809 * cpu_by_arch_id:
810 * @id: Guest-exposed CPU ID of the CPU to obtain.
811 *
812 * Get a CPU with matching @id.
813 *
814 * Returns: The CPU or %NULL if there is no matching CPU.
815 */
816 CPUState *cpu_by_arch_id(int64_t id);
817
818 /**
819 * cpu_throttle_set:
820 * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99.
821 *
822 * Throttles all vcpus by forcing them to sleep for the given percentage of
823 * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly.
824 * (example: 10ms sleep for every 30ms awake).
825 *
826 * cpu_throttle_set can be called as needed to adjust new_throttle_pct.
827 * Once the throttling starts, it will remain in effect until cpu_throttle_stop
828 * is called.
829 */
830 void cpu_throttle_set(int new_throttle_pct);
831
832 /**
833 * cpu_throttle_stop:
834 *
835 * Stops the vcpu throttling started by cpu_throttle_set.
836 */
837 void cpu_throttle_stop(void);
838
839 /**
840 * cpu_throttle_active:
841 *
842 * Returns: %true if the vcpus are currently being throttled, %false otherwise.
843 */
844 bool cpu_throttle_active(void);
845
846 /**
847 * cpu_throttle_get_percentage:
848 *
849 * Returns the vcpu throttle percentage. See cpu_throttle_set for details.
850 *
851 * Returns: The throttle percentage in range 1 to 99.
852 */
853 int cpu_throttle_get_percentage(void);
854
855 #ifndef CONFIG_USER_ONLY
856
857 typedef void (*CPUInterruptHandler)(CPUState *, int);
858
859 extern CPUInterruptHandler cpu_interrupt_handler;
860
861 /**
862 * cpu_interrupt:
863 * @cpu: The CPU to set an interrupt on.
864 * @mask: The interrupts to set.
865 *
866 * Invokes the interrupt handler.
867 */
868 static inline void cpu_interrupt(CPUState *cpu, int mask)
869 {
870 cpu_interrupt_handler(cpu, mask);
871 }
872
873 #else /* USER_ONLY */
874
875 void cpu_interrupt(CPUState *cpu, int mask);
876
877 #endif /* USER_ONLY */
878
879 #ifdef NEED_CPU_H
880
881 #ifdef CONFIG_SOFTMMU
882 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
883 bool is_write, bool is_exec,
884 int opaque, unsigned size)
885 {
886 CPUClass *cc = CPU_GET_CLASS(cpu);
887
888 if (cc->do_unassigned_access) {
889 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
890 }
891 }
892
893 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
894 MMUAccessType access_type,
895 int mmu_idx, uintptr_t retaddr)
896 {
897 CPUClass *cc = CPU_GET_CLASS(cpu);
898
899 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
900 }
901
902 static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
903 vaddr addr, unsigned size,
904 MMUAccessType access_type,
905 int mmu_idx, MemTxAttrs attrs,
906 MemTxResult response,
907 uintptr_t retaddr)
908 {
909 CPUClass *cc = CPU_GET_CLASS(cpu);
910
911 if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_failed) {
912 cc->do_transaction_failed(cpu, physaddr, addr, size, access_type,
913 mmu_idx, attrs, response, retaddr);
914 }
915 }
916 #endif
917
918 #endif /* NEED_CPU_H */
919
920 /**
921 * cpu_set_pc:
922 * @cpu: The CPU to set the program counter for.
923 * @addr: Program counter value.
924 *
925 * Sets the program counter for a CPU.
926 */
927 static inline void cpu_set_pc(CPUState *cpu, vaddr addr)
928 {
929 CPUClass *cc = CPU_GET_CLASS(cpu);
930
931 cc->set_pc(cpu, addr);
932 }
933
934 /**
935 * cpu_reset_interrupt:
936 * @cpu: The CPU to clear the interrupt on.
937 * @mask: The interrupt mask to clear.
938 *
939 * Resets interrupts on the vCPU @cpu.
940 */
941 void cpu_reset_interrupt(CPUState *cpu, int mask);
942
943 /**
944 * cpu_exit:
945 * @cpu: The CPU to exit.
946 *
947 * Requests the CPU @cpu to exit execution.
948 */
949 void cpu_exit(CPUState *cpu);
950
951 /**
952 * cpu_resume:
953 * @cpu: The CPU to resume.
954 *
955 * Resumes CPU, i.e. puts CPU into runnable state.
956 */
957 void cpu_resume(CPUState *cpu);
958
959 /**
960 * cpu_remove:
961 * @cpu: The CPU to remove.
962 *
963 * Requests the CPU to be removed.
964 */
965 void cpu_remove(CPUState *cpu);
966
967 /**
968 * cpu_remove_sync:
969 * @cpu: The CPU to remove.
970 *
971 * Requests the CPU to be removed and waits till it is removed.
972 */
973 void cpu_remove_sync(CPUState *cpu);
974
975 /**
976 * process_queued_cpu_work() - process all items on CPU work queue
977 * @cpu: The CPU which work queue to process.
978 */
979 void process_queued_cpu_work(CPUState *cpu);
980
981 /**
982 * cpu_exec_start:
983 * @cpu: The CPU for the current thread.
984 *
985 * Record that a CPU has started execution and can be interrupted with
986 * cpu_exit.
987 */
988 void cpu_exec_start(CPUState *cpu);
989
990 /**
991 * cpu_exec_end:
992 * @cpu: The CPU for the current thread.
993 *
994 * Record that a CPU has stopped execution and exclusive sections
995 * can be executed without interrupting it.
996 */
997 void cpu_exec_end(CPUState *cpu);
998
999 /**
1000 * start_exclusive:
1001 *
1002 * Wait for a concurrent exclusive section to end, and then start
1003 * a section of work that is run while other CPUs are not running
1004 * between cpu_exec_start and cpu_exec_end. CPUs that are running
1005 * cpu_exec are exited immediately. CPUs that call cpu_exec_start
1006 * during the exclusive section go to sleep until this CPU calls
1007 * end_exclusive.
1008 */
1009 void start_exclusive(void);
1010
1011 /**
1012 * end_exclusive:
1013 *
1014 * Concludes an exclusive execution section started by start_exclusive.
1015 */
1016 void end_exclusive(void);
1017
1018 /**
1019 * qemu_init_vcpu:
1020 * @cpu: The vCPU to initialize.
1021 *
1022 * Initializes a vCPU.
1023 */
1024 void qemu_init_vcpu(CPUState *cpu);
1025
1026 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
1027 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
1028 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
1029
1030 /**
1031 * cpu_single_step:
1032 * @cpu: CPU to the flags for.
1033 * @enabled: Flags to enable.
1034 *
1035 * Enables or disables single-stepping for @cpu.
1036 */
1037 void cpu_single_step(CPUState *cpu, int enabled);
1038
1039 /* Breakpoint/watchpoint flags */
1040 #define BP_MEM_READ 0x01
1041 #define BP_MEM_WRITE 0x02
1042 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
1043 #define BP_STOP_BEFORE_ACCESS 0x04
1044 /* 0x08 currently unused */
1045 #define BP_GDB 0x10
1046 #define BP_CPU 0x20
1047 #define BP_ANY (BP_GDB | BP_CPU)
1048 #define BP_WATCHPOINT_HIT_READ 0x40
1049 #define BP_WATCHPOINT_HIT_WRITE 0x80
1050 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
1051
1052 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
1053 CPUBreakpoint **breakpoint);
1054 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
1055 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
1056 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
1057
1058 /* Return true if PC matches an installed breakpoint. */
1059 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask)
1060 {
1061 CPUBreakpoint *bp;
1062
1063 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) {
1064 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
1065 if (bp->pc == pc && (bp->flags & mask)) {
1066 return true;
1067 }
1068 }
1069 }
1070 return false;
1071 }
1072
1073 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
1074 int flags, CPUWatchpoint **watchpoint);
1075 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
1076 vaddr len, int flags);
1077 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
1078 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
1079
1080 /**
1081 * cpu_get_address_space:
1082 * @cpu: CPU to get address space from
1083 * @asidx: index identifying which address space to get
1084 *
1085 * Return the requested address space of this CPU. @asidx
1086 * specifies which address space to read.
1087 */
1088 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx);
1089
1090 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
1091 GCC_FMT_ATTR(2, 3);
1092 extern Property cpu_common_props[];
1093 void cpu_exec_initfn(CPUState *cpu);
1094 void cpu_exec_realizefn(CPUState *cpu, Error **errp);
1095 void cpu_exec_unrealizefn(CPUState *cpu);
1096
1097 /**
1098 * target_words_bigendian:
1099 * Returns true if the (default) endianness of the target is big endian,
1100 * false otherwise. Note that in target-specific code, you can use
1101 * TARGET_WORDS_BIGENDIAN directly instead. On the other hand, common
1102 * code should normally never need to know about the endianness of the
1103 * target, so please do *not* use this function unless you know very well
1104 * what you are doing!
1105 */
1106 bool target_words_bigendian(void);
1107
1108 #ifdef NEED_CPU_H
1109
1110 #ifdef CONFIG_SOFTMMU
1111 extern const VMStateDescription vmstate_cpu_common;
1112 #else
1113 #define vmstate_cpu_common vmstate_dummy
1114 #endif
1115
1116 #define VMSTATE_CPU() { \
1117 .name = "parent_obj", \
1118 .size = sizeof(CPUState), \
1119 .vmsd = &vmstate_cpu_common, \
1120 .flags = VMS_STRUCT, \
1121 .offset = 0, \
1122 }
1123
1124 #endif /* NEED_CPU_H */
1125
1126 #define UNASSIGNED_CPU_INDEX -1
1127 #define UNASSIGNED_CLUSTER_INDEX -1
1128
1129 #endif