Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request...
[qemu.git] / include / hw / core / tcg-cpu-ops.h
1 /*
2 * TCG CPU-specific operations
3 *
4 * Copyright 2021 SUSE LLC
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9
10 #ifndef TCG_CPU_OPS_H
11 #define TCG_CPU_OPS_H
12
13 #include "hw/core/cpu.h"
14
15 struct TCGCPUOps {
16 /**
17 * @initialize: Initalize TCG state
18 *
19 * Called when the first CPU is realized.
20 */
21 void (*initialize)(void);
22 /**
23 * @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
24 *
25 * This is called when we abandon execution of a TB before starting it,
26 * and must set all parts of the CPU state which the previous TB in the
27 * chain may not have updated.
28 * By default, when this is NULL, a call is made to @set_pc(tb->pc).
29 *
30 * If more state needs to be restored, the target must implement a
31 * function to restore all the state, and register it here.
32 */
33 void (*synchronize_from_tb)(CPUState *cpu, const TranslationBlock *tb);
34 /** @cpu_exec_enter: Callback for cpu_exec preparation */
35 void (*cpu_exec_enter)(CPUState *cpu);
36 /** @cpu_exec_exit: Callback for cpu_exec cleanup */
37 void (*cpu_exec_exit)(CPUState *cpu);
38 /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */
39 bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
40 /**
41 * @do_interrupt: Callback for interrupt handling.
42 *
43 * note that this is in general SOFTMMU only, but it actually isn't
44 * because of an x86 hack (accel/tcg/cpu-exec.c), so we cannot put it
45 * in the SOFTMMU section in general.
46 */
47 void (*do_interrupt)(CPUState *cpu);
48 /**
49 * @tlb_fill: Handle a softmmu tlb miss or user-only address fault
50 *
51 * For system mode, if the access is valid, call tlb_set_page
52 * and return true; if the access is invalid, and probe is
53 * true, return false; otherwise raise an exception and do
54 * not return. For user-only mode, always raise an exception
55 * and do not return.
56 */
57 bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
58 MMUAccessType access_type, int mmu_idx,
59 bool probe, uintptr_t retaddr);
60 /** @debug_excp_handler: Callback for handling debug exceptions */
61 void (*debug_excp_handler)(CPUState *cpu);
62
63 #ifdef NEED_CPU_H
64 #ifdef CONFIG_SOFTMMU
65 /**
66 * @do_transaction_failed: Callback for handling failed memory transactions
67 * (ie bus faults or external aborts; not MMU faults)
68 */
69 void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr,
70 unsigned size, MMUAccessType access_type,
71 int mmu_idx, MemTxAttrs attrs,
72 MemTxResult response, uintptr_t retaddr);
73 /**
74 * @do_unaligned_access: Callback for unaligned access handling
75 */
76 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
77 MMUAccessType access_type,
78 int mmu_idx, uintptr_t retaddr);
79
80 /**
81 * @adjust_watchpoint_address: hack for cpu_check_watchpoint used by ARM
82 */
83 vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
84
85 /**
86 * @debug_check_watchpoint: return true if the architectural
87 * watchpoint whose address has matched should really fire, used by ARM
88 */
89 bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
90
91 /**
92 * @debug_check_breakpoint: return true if the architectural
93 * breakpoint whose PC has matched should really fire.
94 */
95 bool (*debug_check_breakpoint)(CPUState *cpu);
96
97 /**
98 * @io_recompile_replay_branch: Callback for cpu_io_recompile.
99 *
100 * The cpu has been stopped, and cpu_restore_state_from_tb has been
101 * called. If the faulting instruction is in a delay slot, and the
102 * target architecture requires re-execution of the branch, then
103 * adjust the cpu state as required and return true.
104 */
105 bool (*io_recompile_replay_branch)(CPUState *cpu,
106 const TranslationBlock *tb);
107 #endif /* CONFIG_SOFTMMU */
108 #endif /* NEED_CPU_H */
109
110 };
111
112 #endif /* TCG_CPU_OPS_H */