hw/clock: Only propagate clock changes if the clock is changed
[qemu.git] / include / hw / gpio / aspeed_gpio.h
1 /*
2 * ASPEED GPIO Controller
3 *
4 * Copyright (C) 2017-2018 IBM Corp.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #ifndef ASPEED_GPIO_H
11 #define ASPEED_GPIO_H
12
13 #include "hw/sysbus.h"
14
15 #define TYPE_ASPEED_GPIO "aspeed.gpio"
16 #define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO)
17 #define ASPEED_GPIO_CLASS(klass) \
18 OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO)
19 #define ASPEED_GPIO_GET_CLASS(obj) \
20 OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO)
21
22 #define ASPEED_GPIO_MAX_NR_SETS 8
23 #define ASPEED_REGS_PER_BANK 14
24 #define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
25 #define ASPEED_GPIO_NR_PINS 228
26 #define ASPEED_GROUPS_PER_SET 4
27 #define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
28 #define ASPEED_CHARS_PER_GROUP_LABEL 4
29
30 typedef struct GPIOSets GPIOSets;
31
32 typedef struct GPIOSetProperties {
33 uint32_t input;
34 uint32_t output;
35 char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
36 } GPIOSetProperties;
37
38 enum GPIORegType {
39 gpio_not_a_reg,
40 gpio_reg_data_value,
41 gpio_reg_direction,
42 gpio_reg_int_enable,
43 gpio_reg_int_sens_0,
44 gpio_reg_int_sens_1,
45 gpio_reg_int_sens_2,
46 gpio_reg_int_status,
47 gpio_reg_reset_tolerant,
48 gpio_reg_debounce_1,
49 gpio_reg_debounce_2,
50 gpio_reg_cmd_source_0,
51 gpio_reg_cmd_source_1,
52 gpio_reg_data_read,
53 gpio_reg_input_mask,
54 };
55
56 typedef struct AspeedGPIOReg {
57 uint16_t set_idx;
58 enum GPIORegType type;
59 } AspeedGPIOReg;
60
61 typedef struct AspeedGPIOClass {
62 SysBusDevice parent_obj;
63 const GPIOSetProperties *props;
64 uint32_t nr_gpio_pins;
65 uint32_t nr_gpio_sets;
66 uint32_t gap;
67 const AspeedGPIOReg *reg_table;
68 } AspeedGPIOClass;
69
70 typedef struct AspeedGPIOState {
71 /* <private> */
72 SysBusDevice parent;
73
74 /*< public >*/
75 MemoryRegion iomem;
76 int pending;
77 qemu_irq irq;
78 qemu_irq gpios[ASPEED_GPIO_NR_PINS];
79
80 /* Parallel GPIO Registers */
81 uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
82 struct GPIOSets {
83 uint32_t data_value; /* Reflects pin values */
84 uint32_t data_read; /* Contains last value written to data value */
85 uint32_t direction;
86 uint32_t int_enable;
87 uint32_t int_sens_0;
88 uint32_t int_sens_1;
89 uint32_t int_sens_2;
90 uint32_t int_status;
91 uint32_t reset_tol;
92 uint32_t cmd_source_0;
93 uint32_t cmd_source_1;
94 uint32_t debounce_1;
95 uint32_t debounce_2;
96 uint32_t input_mask;
97 } sets[ASPEED_GPIO_MAX_NR_SETS];
98 } AspeedGPIOState;
99
100 #endif /* _ASPEED_GPIO_H_ */