hw/clock: Only propagate clock changes if the clock is changed
[qemu.git] / include / hw / gpio / nrf51_gpio.h
1 /*
2 * nRF51 System-on-Chip general purpose input/output register definition
3 *
4 * QEMU interface:
5 * + sysbus MMIO regions 0: GPIO registers
6 * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin.
7 * Level -1: Externally Disconnected/Floating; Pull-up/down will be regarded
8 * Level 0: Input externally driven LOW
9 * Level 1: Input externally driven HIGH
10 * + Unnamed GPIO outputs 0-31:
11 * Level -1: Disconnected/Floating
12 * Level 0: Driven LOW
13 * Level 1: Driven HIGH
14 *
15 * Accuracy of the peripheral model:
16 * + The nRF51 GPIO output driver supports two modes, standard and high-current
17 * mode. These different drive modes are not modeled and handled the same.
18 * + Pin SENSEing is not modeled/implemented.
19 *
20 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
21 *
22 * This code is licensed under the GPL version 2 or later. See
23 * the COPYING file in the top-level directory.
24 *
25 */
26 #ifndef NRF51_GPIO_H
27 #define NRF51_GPIO_H
28
29 #include "hw/sysbus.h"
30 #define TYPE_NRF51_GPIO "nrf51_soc.gpio"
31 #define NRF51_GPIO(obj) OBJECT_CHECK(NRF51GPIOState, (obj), TYPE_NRF51_GPIO)
32
33 #define NRF51_GPIO_PINS 32
34
35 #define NRF51_GPIO_SIZE 0x1000
36
37 #define NRF51_GPIO_REG_OUT 0x504
38 #define NRF51_GPIO_REG_OUTSET 0x508
39 #define NRF51_GPIO_REG_OUTCLR 0x50C
40 #define NRF51_GPIO_REG_IN 0x510
41 #define NRF51_GPIO_REG_DIR 0x514
42 #define NRF51_GPIO_REG_DIRSET 0x518
43 #define NRF51_GPIO_REG_DIRCLR 0x51C
44 #define NRF51_GPIO_REG_CNF_START 0x700
45 #define NRF51_GPIO_REG_CNF_END 0x77C
46
47 #define NRF51_GPIO_PULLDOWN 1
48 #define NRF51_GPIO_PULLUP 3
49
50 typedef struct NRF51GPIOState {
51 SysBusDevice parent_obj;
52
53 MemoryRegion mmio;
54 qemu_irq irq;
55
56 uint32_t out;
57 uint32_t in;
58 uint32_t in_mask;
59 uint32_t dir;
60 uint32_t cnf[NRF51_GPIO_PINS];
61
62 uint32_t old_out;
63 uint32_t old_out_connected;
64
65 qemu_irq output[NRF51_GPIO_PINS];
66 } NRF51GPIOState;
67
68
69 #endif