block/export: Add query-block-exports
[qemu.git] / include / hw / i386 / ich9.h
1 #ifndef HW_ICH9_H
2 #define HW_ICH9_H
3
4 #include "hw/isa/isa.h"
5 #include "hw/sysbus.h"
6 #include "hw/i386/pc.h"
7 #include "hw/isa/apm.h"
8 #include "hw/pci/pci.h"
9 #include "hw/pci/pcie_host.h"
10 #include "hw/pci/pci_bridge.h"
11 #include "hw/acpi/acpi.h"
12 #include "hw/acpi/ich9.h"
13 #include "hw/pci/pci_bus.h"
14 #include "qom/object.h"
15
16 void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
17 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
18 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
19 void ich9_lpc_pm_init(PCIDevice *pci_lpc, bool smm_enabled);
20 I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
21
22 void ich9_generate_smi(void);
23
24 #define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
25
26 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
27 OBJECT_DECLARE_SIMPLE_TYPE(ICH9LPCState, ICH9_LPC_DEVICE)
28
29 struct ICH9LPCState {
30 /* ICH9 LPC PCI to ISA bridge */
31 PCIDevice d;
32
33 /* (pci device, intx) -> pirq
34 * In real chipset case, the unused slots are never used
35 * as ICH9 supports only D25-D31 irq routing.
36 * On the other hand in qemu case, any slot/function can be populated
37 * via command line option.
38 * So fallback interrupt routing for any devices in any slots is necessary.
39 */
40 uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
41
42 APMState apm;
43 ICH9LPCPMRegs pm;
44 uint32_t sci_level; /* track sci level */
45 uint8_t sci_gsi;
46
47 /* 2.24 Pin Straps */
48 struct {
49 bool spkr_hi;
50 } pin_strap;
51
52 /* 10.1 Chipset Configuration registers(Memory Space)
53 which is pointed by RCBA */
54 uint8_t chip_config[ICH9_CC_SIZE];
55
56 /*
57 * 13.7.5 RST_CNT---Reset Control Register (LPC I/F---D31:F0)
58 *
59 * register contents and IO memory region
60 */
61 uint8_t rst_cnt;
62 MemoryRegion rst_cnt_mem;
63
64 /* SMI feature negotiation via fw_cfg */
65 uint64_t smi_host_features; /* guest-invisible, host endian */
66 uint8_t smi_host_features_le[8]; /* guest-visible, read-only, little
67 * endian uint64_t */
68 uint8_t smi_guest_features_le[8]; /* guest-visible, read-write, little
69 * endian uint64_t */
70 uint8_t smi_features_ok; /* guest-visible, read-only; selecting it
71 * triggers feature lockdown */
72 uint64_t smi_negotiated_features; /* guest-invisible, host endian */
73
74 /* isa bus */
75 ISABus *isa_bus;
76 MemoryRegion rcrb_mem; /* root complex register block */
77 Notifier machine_ready;
78
79 qemu_irq gsi[GSI_NUM_PINS];
80 };
81
82 #define Q35_MASK(bit, ms_bit, ls_bit) \
83 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
84
85 /* ICH9: Chipset Configuration Registers */
86 #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
87
88 #define ICH9_CC
89 #define ICH9_CC_D28IP 0x310C
90 #define ICH9_CC_D28IP_SHIFT 4
91 #define ICH9_CC_D28IP_MASK 0xf
92 #define ICH9_CC_D28IP_DEFAULT 0x00214321
93 #define ICH9_CC_D31IR 0x3140
94 #define ICH9_CC_D30IR 0x3142
95 #define ICH9_CC_D29IR 0x3144
96 #define ICH9_CC_D28IR 0x3146
97 #define ICH9_CC_D27IR 0x3148
98 #define ICH9_CC_D26IR 0x314C
99 #define ICH9_CC_D25IR 0x3150
100 #define ICH9_CC_DIR_DEFAULT 0x3210
101 #define ICH9_CC_D30IR_DEFAULT 0x0
102 #define ICH9_CC_DIR_SHIFT 4
103 #define ICH9_CC_DIR_MASK 0x7
104 #define ICH9_CC_OIC 0x31FF
105 #define ICH9_CC_OIC_AEN 0x1
106 #define ICH9_CC_GCS 0x3410
107 #define ICH9_CC_GCS_DEFAULT 0x00000020
108 #define ICH9_CC_GCS_NO_REBOOT (1 << 5)
109
110 /* D28:F[0-5] */
111 #define ICH9_PCIE_DEV 28
112 #define ICH9_PCIE_FUNC_MAX 6
113
114
115 /* D29:F0 USB UHCI Controller #1 */
116 #define ICH9_USB_UHCI1_DEV 29
117 #define ICH9_USB_UHCI1_FUNC 0
118
119 /* D30:F0 DMI-to-PCI bridge */
120 #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
121 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
122
123 #define ICH9_D2P_BRIDGE_DEV 30
124 #define ICH9_D2P_BRIDGE_FUNC 0
125
126 #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
127
128 #define ICH9_D2P_A2_REVISION 0x92
129
130 /* D31:F0 LPC Processor Interface */
131 #define ICH9_RST_CNT_IOPORT 0xCF9
132
133 /* D31:F1 LPC controller */
134 #define ICH9_A2_LPC "ICH9 A2 LPC"
135 #define ICH9_A2_LPC_SAVEVM_VERSION 0
136
137 #define ICH9_LPC_DEV 31
138 #define ICH9_LPC_FUNC 0
139
140 #define ICH9_A2_LPC_REVISION 0x2
141 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
142
143 #define ICH9_LPC_PMBASE 0x40
144 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
145 #define ICH9_LPC_PMBASE_RTE 0x1
146 #define ICH9_LPC_PMBASE_DEFAULT 0x1
147 #define ICH9_LPC_ACPI_CTRL 0x44
148 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
149 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
150 #define ICH9_LPC_ACPI_CTRL_9 0x0
151 #define ICH9_LPC_ACPI_CTRL_10 0x1
152 #define ICH9_LPC_ACPI_CTRL_11 0x2
153 #define ICH9_LPC_ACPI_CTRL_20 0x4
154 #define ICH9_LPC_ACPI_CTRL_21 0x5
155 #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
156
157 #define ICH9_LPC_PIRQA_ROUT 0x60
158 #define ICH9_LPC_PIRQB_ROUT 0x61
159 #define ICH9_LPC_PIRQC_ROUT 0x62
160 #define ICH9_LPC_PIRQD_ROUT 0x63
161
162 #define ICH9_LPC_PIRQE_ROUT 0x68
163 #define ICH9_LPC_PIRQF_ROUT 0x69
164 #define ICH9_LPC_PIRQG_ROUT 0x6a
165 #define ICH9_LPC_PIRQH_ROUT 0x6b
166
167 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
168 #define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
169 #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
170
171 #define ICH9_LPC_GEN_PMCON_1 0xa0
172 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
173 #define ICH9_LPC_GEN_PMCON_2 0xa2
174 #define ICH9_LPC_GEN_PMCON_3 0xa4
175 #define ICH9_LPC_GEN_PMCON_LOCK 0xa6
176
177 #define ICH9_LPC_RCBA 0xf0
178 #define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
179 #define ICH9_LPC_RCBA_EN 0x1
180 #define ICH9_LPC_RCBA_DEFAULT 0x0
181
182 #define ICH9_LPC_PIC_NUM_PINS 16
183 #define ICH9_LPC_IOAPIC_NUM_PINS 24
184
185 #define ICH9_GPIO_GSI "gsi"
186
187 /* D31:F2 SATA Controller #1 */
188 #define ICH9_SATA1_DEV 31
189 #define ICH9_SATA1_FUNC 2
190
191 /* D31:F0 power management I/O registers
192 offset from the address ICH9_LPC_PMBASE */
193
194 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
195 #define ICH9_PMIO_SIZE 128
196 #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
197
198 #define ICH9_PMIO_PM1_STS 0x00
199 #define ICH9_PMIO_PM1_EN 0x02
200 #define ICH9_PMIO_PM1_CNT 0x04
201 #define ICH9_PMIO_PM1_TMR 0x08
202 #define ICH9_PMIO_GPE0_STS 0x20
203 #define ICH9_PMIO_GPE0_EN 0x28
204 #define ICH9_PMIO_GPE0_LEN 16
205 #define ICH9_PMIO_SMI_EN 0x30
206 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
207 #define ICH9_PMIO_SMI_EN_TCO_EN (1 << 13)
208 #define ICH9_PMIO_SMI_STS 0x34
209 #define ICH9_PMIO_TCO_RLD 0x60
210 #define ICH9_PMIO_TCO_LEN 32
211
212 /* FADT ACPI_ENABLE/ACPI_DISABLE */
213 #define ICH9_APM_ACPI_ENABLE 0x2
214 #define ICH9_APM_ACPI_DISABLE 0x3
215
216
217 /* D31:F3 SMBus controller */
218 #define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
219
220 #define ICH9_A2_SMB_REVISION 0x02
221 #define ICH9_SMB_PI 0x00
222
223 #define ICH9_SMB_SMBMBAR0 0x10
224 #define ICH9_SMB_SMBMBAR1 0x14
225 #define ICH9_SMB_SMBM_BAR 0
226 #define ICH9_SMB_SMBM_SIZE (1 << 8)
227 #define ICH9_SMB_SMB_BASE 0x20
228 #define ICH9_SMB_SMB_BASE_BAR 4
229 #define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
230 #define ICH9_SMB_HOSTC 0x40
231 #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
232 #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
233 #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
234 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
235
236 /* D31:F3 SMBus I/O and memory mapped I/O registers */
237 #define ICH9_SMB_DEV 31
238 #define ICH9_SMB_FUNC 3
239
240 #define ICH9_SMB_HST_STS 0x00
241 #define ICH9_SMB_HST_CNT 0x02
242 #define ICH9_SMB_HST_CMD 0x03
243 #define ICH9_SMB_XMIT_SLVA 0x04
244 #define ICH9_SMB_HST_D0 0x05
245 #define ICH9_SMB_HST_D1 0x06
246 #define ICH9_SMB_HOST_BLOCK_DB 0x07
247
248 #define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features"
249
250 /* bit positions used in fw_cfg SMI feature negotiation */
251 #define ICH9_LPC_SMI_F_BROADCAST_BIT 0
252 #define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1
253 #define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2
254
255 #endif /* HW_ICH9_H */