Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-25-v2' into staging
[qemu.git] / include / hw / i386 / intel_iommu.h
1 /*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef INTEL_IOMMU_H
23 #define INTEL_IOMMU_H
24
25 #include "hw/i386/x86-iommu.h"
26 #include "qemu/iova-tree.h"
27 #include "qom/object.h"
28
29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
30 OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
31
32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region"
33
34 /* DMAR Hardware Unit Definition address (IOMMU unit) */
35 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
36
37 #define VTD_PCI_BUS_MAX 256
38 #define VTD_PCI_SLOT_MAX 32
39 #define VTD_PCI_FUNC_MAX 8
40 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
41 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
42 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
43 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
44
45 #define DMAR_REG_SIZE 0x230
46 #define VTD_HOST_AW_39BIT 39
47 #define VTD_HOST_AW_48BIT 48
48 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT
49 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
50
51 #define DMAR_REPORT_F_INTR (1)
52
53 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
54 #define VTD_MSI_ADDR_HI_SHIFT (32)
55 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
56
57 typedef struct VTDContextEntry VTDContextEntry;
58 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
59 typedef struct VTDAddressSpace VTDAddressSpace;
60 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
61 typedef struct VTDBus VTDBus;
62 typedef union VTD_IR_TableEntry VTD_IR_TableEntry;
63 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress;
64 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry;
65 typedef struct VTDPASIDEntry VTDPASIDEntry;
66
67 /* Context-Entry */
68 struct VTDContextEntry {
69 union {
70 struct {
71 uint64_t lo;
72 uint64_t hi;
73 };
74 struct {
75 uint64_t val[4];
76 };
77 };
78 };
79
80 struct VTDContextCacheEntry {
81 /* The cache entry is obsolete if
82 * context_cache_gen!=IntelIOMMUState.context_cache_gen
83 */
84 uint32_t context_cache_gen;
85 struct VTDContextEntry context_entry;
86 };
87
88 /* PASID Directory Entry */
89 struct VTDPASIDDirEntry {
90 uint64_t val;
91 };
92
93 /* PASID Table Entry */
94 struct VTDPASIDEntry {
95 uint64_t val[8];
96 };
97
98 struct VTDAddressSpace {
99 PCIBus *bus;
100 uint8_t devfn;
101 AddressSpace as;
102 IOMMUMemoryRegion iommu;
103 MemoryRegion root; /* The root container of the device */
104 MemoryRegion nodmar; /* The alias of shared nodmar MR */
105 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */
106 IntelIOMMUState *iommu_state;
107 VTDContextCacheEntry context_cache_entry;
108 QLIST_ENTRY(VTDAddressSpace) next;
109 /* Superset of notifier flags that this address space has */
110 IOMMUNotifierFlag notifier_flags;
111 IOVATree *iova_tree; /* Traces mapped IOVA ranges */
112 };
113
114 struct VTDBus {
115 PCIBus* bus; /* A reference to the bus to provide translation for */
116 /* A table of VTDAddressSpace objects indexed by devfn */
117 VTDAddressSpace *dev_as[];
118 };
119
120 struct VTDIOTLBEntry {
121 uint64_t gfn;
122 uint16_t domain_id;
123 uint64_t slpte;
124 uint64_t mask;
125 uint8_t access_flags;
126 };
127
128 /* VT-d Source-ID Qualifier types */
129 enum {
130 VTD_SQ_FULL = 0x00, /* Full SID verification */
131 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */
132 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */
133 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */
134 VTD_SQ_MAX,
135 };
136
137 /* VT-d Source Validation Types */
138 enum {
139 VTD_SVT_NONE = 0x00, /* No validation */
140 VTD_SVT_ALL = 0x01, /* Do full validation */
141 VTD_SVT_BUS = 0x02, /* Validate bus range */
142 VTD_SVT_MAX,
143 };
144
145 /* Interrupt Remapping Table Entry Definition */
146 union VTD_IR_TableEntry {
147 struct {
148 #ifdef HOST_WORDS_BIGENDIAN
149 uint32_t __reserved_1:8; /* Reserved 1 */
150 uint32_t vector:8; /* Interrupt Vector */
151 uint32_t irte_mode:1; /* IRTE Mode */
152 uint32_t __reserved_0:3; /* Reserved 0 */
153 uint32_t __avail:4; /* Available spaces for software */
154 uint32_t delivery_mode:3; /* Delivery Mode */
155 uint32_t trigger_mode:1; /* Trigger Mode */
156 uint32_t redir_hint:1; /* Redirection Hint */
157 uint32_t dest_mode:1; /* Destination Mode */
158 uint32_t fault_disable:1; /* Fault Processing Disable */
159 uint32_t present:1; /* Whether entry present/available */
160 #else
161 uint32_t present:1; /* Whether entry present/available */
162 uint32_t fault_disable:1; /* Fault Processing Disable */
163 uint32_t dest_mode:1; /* Destination Mode */
164 uint32_t redir_hint:1; /* Redirection Hint */
165 uint32_t trigger_mode:1; /* Trigger Mode */
166 uint32_t delivery_mode:3; /* Delivery Mode */
167 uint32_t __avail:4; /* Available spaces for software */
168 uint32_t __reserved_0:3; /* Reserved 0 */
169 uint32_t irte_mode:1; /* IRTE Mode */
170 uint32_t vector:8; /* Interrupt Vector */
171 uint32_t __reserved_1:8; /* Reserved 1 */
172 #endif
173 uint32_t dest_id; /* Destination ID */
174 uint16_t source_id; /* Source-ID */
175 #ifdef HOST_WORDS_BIGENDIAN
176 uint64_t __reserved_2:44; /* Reserved 2 */
177 uint64_t sid_vtype:2; /* Source-ID Validation Type */
178 uint64_t sid_q:2; /* Source-ID Qualifier */
179 #else
180 uint64_t sid_q:2; /* Source-ID Qualifier */
181 uint64_t sid_vtype:2; /* Source-ID Validation Type */
182 uint64_t __reserved_2:44; /* Reserved 2 */
183 #endif
184 } QEMU_PACKED irte;
185 uint64_t data[2];
186 };
187
188 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */
189 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */
190
191 /* Programming format for MSI/MSI-X addresses */
192 union VTD_IR_MSIAddress {
193 struct {
194 #ifdef HOST_WORDS_BIGENDIAN
195 uint32_t __head:12; /* Should always be: 0x0fee */
196 uint32_t index_l:15; /* Interrupt index bit 14-0 */
197 uint32_t int_mode:1; /* Interrupt format */
198 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
199 uint32_t index_h:1; /* Interrupt index bit 15 */
200 uint32_t __not_care:2;
201 #else
202 uint32_t __not_care:2;
203 uint32_t index_h:1; /* Interrupt index bit 15 */
204 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
205 uint32_t int_mode:1; /* Interrupt format */
206 uint32_t index_l:15; /* Interrupt index bit 14-0 */
207 uint32_t __head:12; /* Should always be: 0x0fee */
208 #endif
209 } QEMU_PACKED addr;
210 uint32_t data;
211 };
212
213 /* When IR is enabled, all MSI/MSI-X data bits should be zero */
214 #define VTD_IR_MSI_DATA (0)
215
216 /* The iommu (DMAR) device state struct */
217 struct IntelIOMMUState {
218 X86IOMMUState x86_iommu;
219 MemoryRegion csrmem;
220 MemoryRegion mr_nodmar;
221 MemoryRegion mr_ir;
222 MemoryRegion mr_sys_alias;
223 uint8_t csr[DMAR_REG_SIZE]; /* register values */
224 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
225 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
226 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
227 uint32_t version;
228
229 bool caching_mode; /* RO - is cap CM enabled? */
230 bool scalable_mode; /* RO - is Scalable Mode supported? */
231
232 dma_addr_t root; /* Current root table pointer */
233 bool root_scalable; /* Type of root table (scalable or not) */
234 bool dmar_enabled; /* Set if DMA remapping is enabled */
235
236 uint16_t iq_head; /* Current invalidation queue head */
237 uint16_t iq_tail; /* Current invalidation queue tail */
238 dma_addr_t iq; /* Current invalidation queue pointer */
239 uint16_t iq_size; /* IQ Size in number of entries */
240 bool iq_dw; /* IQ descriptor width 256bit or not */
241 bool qi_enabled; /* Set if the QI is enabled */
242 uint8_t iq_last_desc_type; /* The type of last completed descriptor */
243
244 /* The index of the Fault Recording Register to be used next.
245 * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
246 */
247 uint16_t next_frcd_reg;
248
249 uint64_t cap; /* The value of capability reg */
250 uint64_t ecap; /* The value of extended capability reg */
251
252 uint32_t context_cache_gen; /* Should be in [1,MAX] */
253 GHashTable *iotlb; /* IOTLB */
254
255 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
256 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
257 /* list of registered notifiers */
258 QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
259
260 /* interrupt remapping */
261 bool intr_enabled; /* Whether guest enabled IR */
262 dma_addr_t intr_root; /* Interrupt remapping table pointer */
263 uint32_t intr_size; /* Number of IR table entries */
264 bool intr_eime; /* Extended interrupt mode enabled */
265 OnOffAuto intr_eim; /* Toggle for EIM cabability */
266 bool buggy_eim; /* Force buggy EIM unless eim=off */
267 uint8_t aw_bits; /* Host/IOVA address width (in bits) */
268 bool dma_drain; /* Whether DMA r/w draining enabled */
269
270 /*
271 * Protects IOMMU states in general. Currently it protects the
272 * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace.
273 */
274 QemuMutex iommu_lock;
275 };
276
277 /* Find the VTD Address space associated with the given bus pointer,
278 * create a new one if none exists
279 */
280 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
281
282 #endif