apic: move target-dependent definitions to cpu.h
[qemu.git] / include / hw / i386 / intel_iommu.h
1 /*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef INTEL_IOMMU_H
23 #define INTEL_IOMMU_H
24 #include "hw/qdev.h"
25 #include "sysemu/dma.h"
26
27 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
28 #define INTEL_IOMMU_DEVICE(obj) \
29 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE)
30
31 /* DMAR Hardware Unit Definition address (IOMMU unit) */
32 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL
33
34 #define VTD_PCI_BUS_MAX 256
35 #define VTD_PCI_SLOT_MAX 32
36 #define VTD_PCI_FUNC_MAX 8
37 #define VTD_PCI_DEVFN_MAX 256
38 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
39 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07)
40 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff)
41 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff)
42
43 #define DMAR_REG_SIZE 0x230
44 #define VTD_HOST_ADDRESS_WIDTH 39
45 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1)
46
47 typedef struct VTDContextEntry VTDContextEntry;
48 typedef struct VTDContextCacheEntry VTDContextCacheEntry;
49 typedef struct IntelIOMMUState IntelIOMMUState;
50 typedef struct VTDAddressSpace VTDAddressSpace;
51 typedef struct VTDIOTLBEntry VTDIOTLBEntry;
52 typedef struct VTDBus VTDBus;
53
54 /* Context-Entry */
55 struct VTDContextEntry {
56 uint64_t lo;
57 uint64_t hi;
58 };
59
60 struct VTDContextCacheEntry {
61 /* The cache entry is obsolete if
62 * context_cache_gen!=IntelIOMMUState.context_cache_gen
63 */
64 uint32_t context_cache_gen;
65 struct VTDContextEntry context_entry;
66 };
67
68 struct VTDAddressSpace {
69 PCIBus *bus;
70 uint8_t devfn;
71 AddressSpace as;
72 MemoryRegion iommu;
73 IntelIOMMUState *iommu_state;
74 VTDContextCacheEntry context_cache_entry;
75 };
76
77 struct VTDBus {
78 PCIBus* bus; /* A reference to the bus to provide translation for */
79 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */
80 };
81
82 struct VTDIOTLBEntry {
83 uint64_t gfn;
84 uint16_t domain_id;
85 uint64_t slpte;
86 uint64_t mask;
87 bool read_flags;
88 bool write_flags;
89 };
90
91 /* The iommu (DMAR) device state struct */
92 struct IntelIOMMUState {
93 SysBusDevice busdev;
94 MemoryRegion csrmem;
95 uint8_t csr[DMAR_REG_SIZE]; /* register values */
96 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */
97 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */
98 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */
99 uint32_t version;
100
101 dma_addr_t root; /* Current root table pointer */
102 bool root_extended; /* Type of root table (extended or not) */
103 bool dmar_enabled; /* Set if DMA remapping is enabled */
104
105 uint16_t iq_head; /* Current invalidation queue head */
106 uint16_t iq_tail; /* Current invalidation queue tail */
107 dma_addr_t iq; /* Current invalidation queue pointer */
108 uint16_t iq_size; /* IQ Size in number of entries */
109 bool qi_enabled; /* Set if the QI is enabled */
110 uint8_t iq_last_desc_type; /* The type of last completed descriptor */
111
112 /* The index of the Fault Recording Register to be used next.
113 * Wraps around from N-1 to 0, where N is the number of FRCD_REG.
114 */
115 uint16_t next_frcd_reg;
116
117 uint64_t cap; /* The value of capability reg */
118 uint64_t ecap; /* The value of extended capability reg */
119
120 uint32_t context_cache_gen; /* Should be in [1,MAX] */
121 GHashTable *iotlb; /* IOTLB */
122
123 MemoryRegionIOMMUOps iommu_ops;
124 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */
125 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */
126 };
127
128 /* Find the VTD Address space associated with the given bus pointer,
129 * create a new one if none exists
130 */
131 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn);
132
133 #endif