apic: move target-dependent definitions to cpu.h
[qemu.git] / include / hw / i386 / ioapic_internal.h
1 /*
2 * IOAPIC emulation logic - internal interfaces
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2009 Xiantao Zhang, Intel
6 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef QEMU_IOAPIC_INTERNAL_H
23 #define QEMU_IOAPIC_INTERNAL_H
24
25 #include "hw/hw.h"
26 #include "exec/memory.h"
27 #include "hw/sysbus.h"
28
29 #define MAX_IOAPICS 1
30
31 #define IOAPIC_VERSION 0x11
32
33 #define IOAPIC_LVT_DEST_SHIFT 56
34 #define IOAPIC_LVT_MASKED_SHIFT 16
35 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
36 #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
37 #define IOAPIC_LVT_POLARITY_SHIFT 13
38 #define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
39 #define IOAPIC_LVT_DEST_MODE_SHIFT 11
40 #define IOAPIC_LVT_DELIV_MODE_SHIFT 8
41
42 #define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
43 #define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
44 #define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
45 #define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT)
46 #define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
47 #define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
48 #define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
49
50 #define IOAPIC_TRIGGER_EDGE 0
51 #define IOAPIC_TRIGGER_LEVEL 1
52
53 /*io{apic,sapic} delivery mode*/
54 #define IOAPIC_DM_FIXED 0x0
55 #define IOAPIC_DM_LOWEST_PRIORITY 0x1
56 #define IOAPIC_DM_PMI 0x2
57 #define IOAPIC_DM_NMI 0x4
58 #define IOAPIC_DM_INIT 0x5
59 #define IOAPIC_DM_SIPI 0x6
60 #define IOAPIC_DM_EXTINT 0x7
61 #define IOAPIC_DM_MASK 0x7
62
63 #define IOAPIC_VECTOR_MASK 0xff
64
65 #define IOAPIC_IOREGSEL 0x00
66 #define IOAPIC_IOWIN 0x10
67
68 #define IOAPIC_REG_ID 0x00
69 #define IOAPIC_REG_VER 0x01
70 #define IOAPIC_REG_ARB 0x02
71 #define IOAPIC_REG_REDTBL_BASE 0x10
72 #define IOAPIC_ID 0x00
73
74 #define IOAPIC_ID_SHIFT 24
75 #define IOAPIC_ID_MASK 0xf
76
77 #define IOAPIC_VER_ENTRIES_SHIFT 16
78
79 typedef struct IOAPICCommonState IOAPICCommonState;
80
81 #define TYPE_IOAPIC_COMMON "ioapic-common"
82 #define IOAPIC_COMMON(obj) \
83 OBJECT_CHECK(IOAPICCommonState, (obj), TYPE_IOAPIC_COMMON)
84 #define IOAPIC_COMMON_CLASS(klass) \
85 OBJECT_CLASS_CHECK(IOAPICCommonClass, (klass), TYPE_IOAPIC_COMMON)
86 #define IOAPIC_COMMON_GET_CLASS(obj) \
87 OBJECT_GET_CLASS(IOAPICCommonClass, (obj), TYPE_IOAPIC_COMMON)
88
89 typedef struct IOAPICCommonClass {
90 SysBusDeviceClass parent_class;
91
92 DeviceRealize realize;
93 void (*pre_save)(IOAPICCommonState *s);
94 void (*post_load)(IOAPICCommonState *s);
95 } IOAPICCommonClass;
96
97 struct IOAPICCommonState {
98 SysBusDevice busdev;
99 MemoryRegion io_memory;
100 uint8_t id;
101 uint8_t ioregsel;
102 uint32_t irr;
103 uint64_t ioredtbl[IOAPIC_NUM_PINS];
104 };
105
106 void ioapic_reset_common(DeviceState *dev);
107
108 void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
109
110 #endif /* !QEMU_IOAPIC_INTERNAL_H */