ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / i386 / ioapic_internal.h
1 /*
2 * IOAPIC emulation logic - internal interfaces
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2009 Xiantao Zhang, Intel
6 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #ifndef QEMU_IOAPIC_INTERNAL_H
23 #define QEMU_IOAPIC_INTERNAL_H
24
25 #include "exec/memory.h"
26 #include "hw/sysbus.h"
27 #include "qemu/notify.h"
28
29 #define MAX_IOAPICS 1
30
31 #define IOAPIC_LVT_DEST_SHIFT 56
32 #define IOAPIC_LVT_DEST_IDX_SHIFT 48
33 #define IOAPIC_LVT_MASKED_SHIFT 16
34 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
35 #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
36 #define IOAPIC_LVT_POLARITY_SHIFT 13
37 #define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
38 #define IOAPIC_LVT_DEST_MODE_SHIFT 11
39 #define IOAPIC_LVT_DELIV_MODE_SHIFT 8
40
41 #define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
42 #define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
43 #define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
44 #define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT)
45 #define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
46 #define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
47 #define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
48
49 /* Bits that are read-only for IOAPIC entry */
50 #define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \
51 IOAPIC_LVT_DELIV_STATUS)
52 #define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS)
53
54 #define IOAPIC_TRIGGER_EDGE 0
55 #define IOAPIC_TRIGGER_LEVEL 1
56
57 /*io{apic,sapic} delivery mode*/
58 #define IOAPIC_DM_FIXED 0x0
59 #define IOAPIC_DM_LOWEST_PRIORITY 0x1
60 #define IOAPIC_DM_PMI 0x2
61 #define IOAPIC_DM_NMI 0x4
62 #define IOAPIC_DM_INIT 0x5
63 #define IOAPIC_DM_SIPI 0x6
64 #define IOAPIC_DM_EXTINT 0x7
65 #define IOAPIC_DM_MASK 0x7
66
67 #define IOAPIC_VECTOR_MASK 0xff
68
69 #define IOAPIC_IOREGSEL 0x00
70 #define IOAPIC_IOWIN 0x10
71 #define IOAPIC_EOI 0x40
72
73 #define IOAPIC_REG_ID 0x00
74 #define IOAPIC_REG_VER 0x01
75 #define IOAPIC_REG_ARB 0x02
76 #define IOAPIC_REG_REDTBL_BASE 0x10
77 #define IOAPIC_ID 0x00
78
79 #define IOAPIC_ID_SHIFT 24
80 #define IOAPIC_ID_MASK 0xf
81
82 #define IOAPIC_VER_ENTRIES_SHIFT 16
83
84 typedef struct IOAPICCommonState IOAPICCommonState;
85
86 #define TYPE_IOAPIC_COMMON "ioapic-common"
87 #define IOAPIC_COMMON(obj) \
88 OBJECT_CHECK(IOAPICCommonState, (obj), TYPE_IOAPIC_COMMON)
89 #define IOAPIC_COMMON_CLASS(klass) \
90 OBJECT_CLASS_CHECK(IOAPICCommonClass, (klass), TYPE_IOAPIC_COMMON)
91 #define IOAPIC_COMMON_GET_CLASS(obj) \
92 OBJECT_GET_CLASS(IOAPICCommonClass, (obj), TYPE_IOAPIC_COMMON)
93
94 typedef struct IOAPICCommonClass {
95 SysBusDeviceClass parent_class;
96
97 DeviceRealize realize;
98 DeviceUnrealize unrealize;
99 void (*pre_save)(IOAPICCommonState *s);
100 void (*post_load)(IOAPICCommonState *s);
101 } IOAPICCommonClass;
102
103 struct IOAPICCommonState {
104 SysBusDevice busdev;
105 MemoryRegion io_memory;
106 uint8_t id;
107 uint8_t ioregsel;
108 uint32_t irr;
109 uint64_t ioredtbl[IOAPIC_NUM_PINS];
110 Notifier machine_done;
111 uint8_t version;
112 uint64_t irq_count[IOAPIC_NUM_PINS];
113 int irq_level[IOAPIC_NUM_PINS];
114 int irq_eoi[IOAPIC_NUM_PINS];
115 QEMUTimer *delayed_ioapic_service_timer;
116 };
117
118 void ioapic_reset_common(DeviceState *dev);
119
120 void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s);
121 void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
122
123 #endif /* QEMU_IOAPIC_INTERNAL_H */