pc: Support firmware configuration with -blockdev
[qemu.git] / include / hw / i386 / pc.h
1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu-common.h"
5 #include "exec/memory.h"
6 #include "hw/boards.h"
7 #include "hw/isa/isa.h"
8 #include "hw/block/fdc.h"
9 #include "hw/block/flash.h"
10 #include "net/net.h"
11 #include "hw/i386/ioapic.h"
12
13 #include "qemu/range.h"
14 #include "qemu/bitmap.h"
15 #include "sysemu/sysemu.h"
16 #include "hw/pci/pci.h"
17 #include "hw/mem/pc-dimm.h"
18 #include "hw/mem/nvdimm.h"
19 #include "hw/acpi/acpi_dev_interface.h"
20
21 #define HPET_INTCAP "hpet-intcap"
22
23 /**
24 * PCMachineState:
25 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
26 * @boot_cpus: number of present VCPUs
27 */
28 struct PCMachineState {
29 /*< private >*/
30 MachineState parent_obj;
31
32 /* <public> */
33
34 /* State for other subsystems/APIs: */
35 Notifier machine_done;
36
37 /* Pointers to devices and objects: */
38 HotplugHandler *acpi_dev;
39 ISADevice *rtc;
40 PCIBus *bus;
41 FWCfgState *fw_cfg;
42 qemu_irq *gsi;
43 PFlashCFI01 *flash[2];
44
45 /* Configuration options: */
46 uint64_t max_ram_below_4g;
47 OnOffAuto vmport;
48 OnOffAuto smm;
49
50 AcpiNVDIMMState acpi_nvdimm_state;
51
52 bool acpi_build_enabled;
53 bool smbus_enabled;
54 bool sata_enabled;
55 bool pit_enabled;
56
57 /* RAM information (sizes, addresses, configuration): */
58 ram_addr_t below_4g_mem_size, above_4g_mem_size;
59
60 /* CPU and apic information: */
61 bool apic_xrupt_override;
62 unsigned apic_id_limit;
63 uint16_t boot_cpus;
64
65 /* NUMA information: */
66 uint64_t numa_nodes;
67 uint64_t *node_mem;
68
69 /* Address space used by IOAPIC device. All IOAPIC interrupts
70 * will be translated to MSI messages in the address space. */
71 AddressSpace *ioapic_as;
72 };
73
74 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
75 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
76 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
77 #define PC_MACHINE_VMPORT "vmport"
78 #define PC_MACHINE_SMM "smm"
79 #define PC_MACHINE_NVDIMM "nvdimm"
80 #define PC_MACHINE_NVDIMM_PERSIST "nvdimm-persistence"
81 #define PC_MACHINE_SMBUS "smbus"
82 #define PC_MACHINE_SATA "sata"
83 #define PC_MACHINE_PIT "pit"
84
85 /**
86 * PCMachineClass:
87 *
88 * Compat fields:
89 *
90 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
91 * backend's alignment value if provided
92 * @acpi_data_size: Size of the chunk of memory at the top of RAM
93 * for the BIOS ACPI tables and other BIOS
94 * datastructures.
95 * @gigabyte_align: Make sure that guest addresses aligned at
96 * 1Gbyte boundaries get mapped to host
97 * addresses aligned at 1Gbyte boundaries. This
98 * way we can use 1GByte pages in the host.
99 *
100 */
101 typedef struct PCMachineClass {
102 /*< private >*/
103 MachineClass parent_class;
104
105 /*< public >*/
106
107 /* Device configuration: */
108 bool pci_enabled;
109 bool kvmclock_enabled;
110 const char *default_nic_model;
111
112 /* Compat options: */
113
114 /* ACPI compat: */
115 bool has_acpi_build;
116 bool rsdp_in_ram;
117 int legacy_acpi_table_size;
118 unsigned acpi_data_size;
119
120 /* SMBIOS compat: */
121 bool smbios_defaults;
122 bool smbios_legacy_mode;
123 bool smbios_uuid_encoded;
124
125 /* RAM / address space compat: */
126 bool gigabyte_align;
127 bool has_reserved_memory;
128 bool enforce_aligned_dimm;
129 bool broken_reserved_end;
130
131 /* TSC rate migration: */
132 bool save_tsc_khz;
133 /* generate legacy CPU hotplug AML */
134 bool legacy_cpu_hotplug;
135
136 /* use DMA capable linuxboot option rom */
137 bool linuxboot_dma_enabled;
138
139 /* use PVH to load kernels that support this feature */
140 bool pvh_enabled;
141 } PCMachineClass;
142
143 #define TYPE_PC_MACHINE "generic-pc-machine"
144 #define PC_MACHINE(obj) \
145 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
146 #define PC_MACHINE_GET_CLASS(obj) \
147 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
148 #define PC_MACHINE_CLASS(klass) \
149 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
150
151 /* i8259.c */
152
153 extern DeviceState *isa_pic;
154 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
155 qemu_irq *kvm_i8259_init(ISABus *bus);
156 int pic_read_irq(DeviceState *d);
157 int pic_get_output(DeviceState *d);
158
159 /* ioapic.c */
160
161 /* Global System Interrupts */
162
163 #define GSI_NUM_PINS IOAPIC_NUM_PINS
164
165 typedef struct GSIState {
166 qemu_irq i8259_irq[ISA_NUM_IRQS];
167 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
168 } GSIState;
169
170 void gsi_handler(void *opaque, int n, int level);
171
172 /* vmport.c */
173 #define TYPE_VMPORT "vmport"
174 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
175
176 static inline void vmport_init(ISABus *bus)
177 {
178 isa_create_simple(bus, TYPE_VMPORT);
179 }
180
181 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
182 void vmmouse_get_data(uint32_t *data);
183 void vmmouse_set_data(const uint32_t *data);
184
185 /* pc.c */
186 extern int fd_bootchk;
187
188 bool pc_machine_is_smm_enabled(PCMachineState *pcms);
189 void pc_register_ferr_irq(qemu_irq irq);
190 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
191
192 void pc_cpus_init(PCMachineState *pcms);
193 void pc_hot_add_cpu(const int64_t id, Error **errp);
194
195 void pc_guest_info_init(PCMachineState *pcms);
196
197 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
198 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
199 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
200 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
201 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
202 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
203 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
204
205
206 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
207 MemoryRegion *pci_address_space);
208
209 void xen_load_linux(PCMachineState *pcms);
210 void pc_memory_init(PCMachineState *pcms,
211 MemoryRegion *system_memory,
212 MemoryRegion *rom_memory,
213 MemoryRegion **ram_memory);
214 uint64_t pc_pci_hole64_start(void);
215 qemu_irq pc_allocate_cpu_irq(void);
216 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
217 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
218 ISADevice **rtc_state,
219 bool create_fdctrl,
220 bool no_vmport,
221 bool has_pit,
222 uint32_t hpet_irqs);
223 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
224 void pc_cmos_init(PCMachineState *pcms,
225 BusState *ide0, BusState *ide1,
226 ISADevice *s);
227 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
228 void pc_pci_device_init(PCIBus *pci_bus);
229
230 typedef void (*cpu_set_smm_t)(int smm, void *arg);
231
232 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
233
234 ISADevice *pc_find_fdc0(void);
235 int cmos_get_fd_drive_type(FloppyDriveType fd0);
236
237 #define FW_CFG_IO_BASE 0x510
238
239 #define PORT92_A20_LINE "a20"
240
241 /* acpi_piix.c */
242
243 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
244 qemu_irq sci_irq, qemu_irq smi_irq,
245 int smm_enabled, DeviceState **piix4_pm);
246
247 /* hpet.c */
248 extern int no_hpet;
249
250 /* piix_pci.c */
251 struct PCII440FXState;
252 typedef struct PCII440FXState PCII440FXState;
253
254 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
255 #define TYPE_I440FX_PCI_DEVICE "i440FX"
256
257 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
258
259 /*
260 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
261 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
262 */
263 #define RCR_IOPORT 0xcf9
264
265 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
266 PCII440FXState **pi440fx_state, int *piix_devfn,
267 ISABus **isa_bus, qemu_irq *pic,
268 MemoryRegion *address_space_mem,
269 MemoryRegion *address_space_io,
270 ram_addr_t ram_size,
271 ram_addr_t below_4g_mem_size,
272 ram_addr_t above_4g_mem_size,
273 MemoryRegion *pci_memory,
274 MemoryRegion *ram_memory);
275
276 PCIBus *find_i440fx(void);
277 /* piix4.c */
278 extern PCIDevice *piix4_dev;
279 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
280
281 /* pc_sysfw.c */
282 void pc_system_flash_create(PCMachineState *pcms);
283 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
284
285 /* acpi-build.c */
286 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
287 const CPUArchIdList *apic_ids, GArray *entry);
288
289 /* e820 types */
290 #define E820_RAM 1
291 #define E820_RESERVED 2
292 #define E820_ACPI 3
293 #define E820_NVS 4
294 #define E820_UNUSABLE 5
295
296 int e820_add_entry(uint64_t, uint64_t, uint32_t);
297 int e820_get_num_entries(void);
298 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
299
300 extern GlobalProperty pc_compat_3_1[];
301 extern const size_t pc_compat_3_1_len;
302
303 extern GlobalProperty pc_compat_3_0[];
304 extern const size_t pc_compat_3_0_len;
305
306 extern GlobalProperty pc_compat_2_12[];
307 extern const size_t pc_compat_2_12_len;
308
309 extern GlobalProperty pc_compat_2_11[];
310 extern const size_t pc_compat_2_11_len;
311
312 extern GlobalProperty pc_compat_2_10[];
313 extern const size_t pc_compat_2_10_len;
314
315 extern GlobalProperty pc_compat_2_9[];
316 extern const size_t pc_compat_2_9_len;
317
318 extern GlobalProperty pc_compat_2_8[];
319 extern const size_t pc_compat_2_8_len;
320
321 extern GlobalProperty pc_compat_2_7[];
322 extern const size_t pc_compat_2_7_len;
323
324 extern GlobalProperty pc_compat_2_6[];
325 extern const size_t pc_compat_2_6_len;
326
327 extern GlobalProperty pc_compat_2_5[];
328 extern const size_t pc_compat_2_5_len;
329
330 extern GlobalProperty pc_compat_2_4[];
331 extern const size_t pc_compat_2_4_len;
332
333 extern GlobalProperty pc_compat_2_3[];
334 extern const size_t pc_compat_2_3_len;
335
336 extern GlobalProperty pc_compat_2_2[];
337 extern const size_t pc_compat_2_2_len;
338
339 extern GlobalProperty pc_compat_2_1[];
340 extern const size_t pc_compat_2_1_len;
341
342 extern GlobalProperty pc_compat_2_0[];
343 extern const size_t pc_compat_2_0_len;
344
345 extern GlobalProperty pc_compat_1_7[];
346 extern const size_t pc_compat_1_7_len;
347
348 extern GlobalProperty pc_compat_1_6[];
349 extern const size_t pc_compat_1_6_len;
350
351 extern GlobalProperty pc_compat_1_5[];
352 extern const size_t pc_compat_1_5_len;
353
354 extern GlobalProperty pc_compat_1_4[];
355 extern const size_t pc_compat_1_4_len;
356
357 /* Helper for setting model-id for CPU models that changed model-id
358 * depending on QEMU versions up to QEMU 2.4.
359 */
360 #define PC_CPU_MODEL_IDS(v) \
361 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
362 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
363 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
364
365 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
366 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
367 { \
368 MachineClass *mc = MACHINE_CLASS(oc); \
369 optsfn(mc); \
370 mc->init = initfn; \
371 } \
372 static const TypeInfo pc_machine_type_##suffix = { \
373 .name = namestr TYPE_MACHINE_SUFFIX, \
374 .parent = TYPE_PC_MACHINE, \
375 .class_init = pc_machine_##suffix##_class_init, \
376 }; \
377 static void pc_machine_init_##suffix(void) \
378 { \
379 type_register(&pc_machine_type_##suffix); \
380 } \
381 type_init(pc_machine_init_##suffix)
382
383 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
384 #endif