pc_sysfw: Pass PCMachineState to pc_system_firmware_init()
[qemu.git] / include / hw / i386 / pc.h
1 #ifndef HW_PC_H
2 #define HW_PC_H
3
4 #include "qemu-common.h"
5 #include "exec/memory.h"
6 #include "hw/boards.h"
7 #include "hw/isa/isa.h"
8 #include "hw/block/fdc.h"
9 #include "net/net.h"
10 #include "hw/i386/ioapic.h"
11
12 #include "qemu/range.h"
13 #include "qemu/bitmap.h"
14 #include "sysemu/sysemu.h"
15 #include "hw/pci/pci.h"
16 #include "hw/mem/pc-dimm.h"
17 #include "hw/mem/nvdimm.h"
18 #include "hw/acpi/acpi_dev_interface.h"
19
20 #define HPET_INTCAP "hpet-intcap"
21
22 /**
23 * PCMachineState:
24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
25 * @boot_cpus: number of present VCPUs
26 */
27 struct PCMachineState {
28 /*< private >*/
29 MachineState parent_obj;
30
31 /* <public> */
32
33 /* State for other subsystems/APIs: */
34 Notifier machine_done;
35
36 /* Pointers to devices and objects: */
37 HotplugHandler *acpi_dev;
38 ISADevice *rtc;
39 PCIBus *bus;
40 FWCfgState *fw_cfg;
41 qemu_irq *gsi;
42
43 /* Configuration options: */
44 uint64_t max_ram_below_4g;
45 OnOffAuto vmport;
46 OnOffAuto smm;
47
48 AcpiNVDIMMState acpi_nvdimm_state;
49
50 bool acpi_build_enabled;
51 bool smbus_enabled;
52 bool sata_enabled;
53 bool pit_enabled;
54
55 /* RAM information (sizes, addresses, configuration): */
56 ram_addr_t below_4g_mem_size, above_4g_mem_size;
57
58 /* CPU and apic information: */
59 bool apic_xrupt_override;
60 unsigned apic_id_limit;
61 uint16_t boot_cpus;
62
63 /* NUMA information: */
64 uint64_t numa_nodes;
65 uint64_t *node_mem;
66
67 /* Address space used by IOAPIC device. All IOAPIC interrupts
68 * will be translated to MSI messages in the address space. */
69 AddressSpace *ioapic_as;
70 };
71
72 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
73 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
74 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
75 #define PC_MACHINE_VMPORT "vmport"
76 #define PC_MACHINE_SMM "smm"
77 #define PC_MACHINE_NVDIMM "nvdimm"
78 #define PC_MACHINE_NVDIMM_PERSIST "nvdimm-persistence"
79 #define PC_MACHINE_SMBUS "smbus"
80 #define PC_MACHINE_SATA "sata"
81 #define PC_MACHINE_PIT "pit"
82
83 /**
84 * PCMachineClass:
85 *
86 * Compat fields:
87 *
88 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
89 * backend's alignment value if provided
90 * @acpi_data_size: Size of the chunk of memory at the top of RAM
91 * for the BIOS ACPI tables and other BIOS
92 * datastructures.
93 * @gigabyte_align: Make sure that guest addresses aligned at
94 * 1Gbyte boundaries get mapped to host
95 * addresses aligned at 1Gbyte boundaries. This
96 * way we can use 1GByte pages in the host.
97 *
98 */
99 typedef struct PCMachineClass {
100 /*< private >*/
101 MachineClass parent_class;
102
103 /*< public >*/
104
105 /* Device configuration: */
106 bool pci_enabled;
107 bool kvmclock_enabled;
108 const char *default_nic_model;
109
110 /* Compat options: */
111
112 /* ACPI compat: */
113 bool has_acpi_build;
114 bool rsdp_in_ram;
115 int legacy_acpi_table_size;
116 unsigned acpi_data_size;
117
118 /* SMBIOS compat: */
119 bool smbios_defaults;
120 bool smbios_legacy_mode;
121 bool smbios_uuid_encoded;
122
123 /* RAM / address space compat: */
124 bool gigabyte_align;
125 bool has_reserved_memory;
126 bool enforce_aligned_dimm;
127 bool broken_reserved_end;
128
129 /* TSC rate migration: */
130 bool save_tsc_khz;
131 /* generate legacy CPU hotplug AML */
132 bool legacy_cpu_hotplug;
133
134 /* use DMA capable linuxboot option rom */
135 bool linuxboot_dma_enabled;
136
137 /* use PVH to load kernels that support this feature */
138 bool pvh_enabled;
139 } PCMachineClass;
140
141 #define TYPE_PC_MACHINE "generic-pc-machine"
142 #define PC_MACHINE(obj) \
143 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
144 #define PC_MACHINE_GET_CLASS(obj) \
145 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
146 #define PC_MACHINE_CLASS(klass) \
147 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
148
149 /* i8259.c */
150
151 extern DeviceState *isa_pic;
152 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
153 qemu_irq *kvm_i8259_init(ISABus *bus);
154 int pic_read_irq(DeviceState *d);
155 int pic_get_output(DeviceState *d);
156
157 /* ioapic.c */
158
159 /* Global System Interrupts */
160
161 #define GSI_NUM_PINS IOAPIC_NUM_PINS
162
163 typedef struct GSIState {
164 qemu_irq i8259_irq[ISA_NUM_IRQS];
165 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
166 } GSIState;
167
168 void gsi_handler(void *opaque, int n, int level);
169
170 /* vmport.c */
171 #define TYPE_VMPORT "vmport"
172 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
173
174 static inline void vmport_init(ISABus *bus)
175 {
176 isa_create_simple(bus, TYPE_VMPORT);
177 }
178
179 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
180 void vmmouse_get_data(uint32_t *data);
181 void vmmouse_set_data(const uint32_t *data);
182
183 /* pc.c */
184 extern int fd_bootchk;
185
186 bool pc_machine_is_smm_enabled(PCMachineState *pcms);
187 void pc_register_ferr_irq(qemu_irq irq);
188 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
189
190 void pc_cpus_init(PCMachineState *pcms);
191 void pc_hot_add_cpu(const int64_t id, Error **errp);
192
193 void pc_guest_info_init(PCMachineState *pcms);
194
195 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
196 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
197 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
198 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
199 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
200 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
201 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
202
203
204 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
205 MemoryRegion *pci_address_space);
206
207 void xen_load_linux(PCMachineState *pcms);
208 void pc_memory_init(PCMachineState *pcms,
209 MemoryRegion *system_memory,
210 MemoryRegion *rom_memory,
211 MemoryRegion **ram_memory);
212 uint64_t pc_pci_hole64_start(void);
213 qemu_irq pc_allocate_cpu_irq(void);
214 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
215 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
216 ISADevice **rtc_state,
217 bool create_fdctrl,
218 bool no_vmport,
219 bool has_pit,
220 uint32_t hpet_irqs);
221 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
222 void pc_cmos_init(PCMachineState *pcms,
223 BusState *ide0, BusState *ide1,
224 ISADevice *s);
225 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
226 void pc_pci_device_init(PCIBus *pci_bus);
227
228 typedef void (*cpu_set_smm_t)(int smm, void *arg);
229
230 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
231
232 ISADevice *pc_find_fdc0(void);
233 int cmos_get_fd_drive_type(FloppyDriveType fd0);
234
235 #define FW_CFG_IO_BASE 0x510
236
237 #define PORT92_A20_LINE "a20"
238
239 /* acpi_piix.c */
240
241 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
242 qemu_irq sci_irq, qemu_irq smi_irq,
243 int smm_enabled, DeviceState **piix4_pm);
244
245 /* hpet.c */
246 extern int no_hpet;
247
248 /* piix_pci.c */
249 struct PCII440FXState;
250 typedef struct PCII440FXState PCII440FXState;
251
252 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
253 #define TYPE_I440FX_PCI_DEVICE "i440FX"
254
255 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
256
257 /*
258 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
259 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
260 */
261 #define RCR_IOPORT 0xcf9
262
263 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
264 PCII440FXState **pi440fx_state, int *piix_devfn,
265 ISABus **isa_bus, qemu_irq *pic,
266 MemoryRegion *address_space_mem,
267 MemoryRegion *address_space_io,
268 ram_addr_t ram_size,
269 ram_addr_t below_4g_mem_size,
270 ram_addr_t above_4g_mem_size,
271 MemoryRegion *pci_memory,
272 MemoryRegion *ram_memory);
273
274 PCIBus *find_i440fx(void);
275 /* piix4.c */
276 extern PCIDevice *piix4_dev;
277 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
278
279 /* pc_sysfw.c */
280 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
281
282 /* acpi-build.c */
283 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
284 const CPUArchIdList *apic_ids, GArray *entry);
285
286 /* e820 types */
287 #define E820_RAM 1
288 #define E820_RESERVED 2
289 #define E820_ACPI 3
290 #define E820_NVS 4
291 #define E820_UNUSABLE 5
292
293 int e820_add_entry(uint64_t, uint64_t, uint32_t);
294 int e820_get_num_entries(void);
295 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
296
297 extern GlobalProperty pc_compat_3_1[];
298 extern const size_t pc_compat_3_1_len;
299
300 extern GlobalProperty pc_compat_3_0[];
301 extern const size_t pc_compat_3_0_len;
302
303 extern GlobalProperty pc_compat_2_12[];
304 extern const size_t pc_compat_2_12_len;
305
306 extern GlobalProperty pc_compat_2_11[];
307 extern const size_t pc_compat_2_11_len;
308
309 extern GlobalProperty pc_compat_2_10[];
310 extern const size_t pc_compat_2_10_len;
311
312 extern GlobalProperty pc_compat_2_9[];
313 extern const size_t pc_compat_2_9_len;
314
315 extern GlobalProperty pc_compat_2_8[];
316 extern const size_t pc_compat_2_8_len;
317
318 extern GlobalProperty pc_compat_2_7[];
319 extern const size_t pc_compat_2_7_len;
320
321 extern GlobalProperty pc_compat_2_6[];
322 extern const size_t pc_compat_2_6_len;
323
324 extern GlobalProperty pc_compat_2_5[];
325 extern const size_t pc_compat_2_5_len;
326
327 extern GlobalProperty pc_compat_2_4[];
328 extern const size_t pc_compat_2_4_len;
329
330 extern GlobalProperty pc_compat_2_3[];
331 extern const size_t pc_compat_2_3_len;
332
333 extern GlobalProperty pc_compat_2_2[];
334 extern const size_t pc_compat_2_2_len;
335
336 extern GlobalProperty pc_compat_2_1[];
337 extern const size_t pc_compat_2_1_len;
338
339 extern GlobalProperty pc_compat_2_0[];
340 extern const size_t pc_compat_2_0_len;
341
342 extern GlobalProperty pc_compat_1_7[];
343 extern const size_t pc_compat_1_7_len;
344
345 extern GlobalProperty pc_compat_1_6[];
346 extern const size_t pc_compat_1_6_len;
347
348 extern GlobalProperty pc_compat_1_5[];
349 extern const size_t pc_compat_1_5_len;
350
351 extern GlobalProperty pc_compat_1_4[];
352 extern const size_t pc_compat_1_4_len;
353
354 /* Helper for setting model-id for CPU models that changed model-id
355 * depending on QEMU versions up to QEMU 2.4.
356 */
357 #define PC_CPU_MODEL_IDS(v) \
358 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
359 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
360 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
361
362 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
363 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
364 { \
365 MachineClass *mc = MACHINE_CLASS(oc); \
366 optsfn(mc); \
367 mc->init = initfn; \
368 } \
369 static const TypeInfo pc_machine_type_##suffix = { \
370 .name = namestr TYPE_MACHINE_SUFFIX, \
371 .parent = TYPE_PC_MACHINE, \
372 .class_init = pc_machine_##suffix##_class_init, \
373 }; \
374 static void pc_machine_init_##suffix(void) \
375 { \
376 type_register(&pc_machine_type_##suffix); \
377 } \
378 type_init(pc_machine_init_##suffix)
379
380 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
381 #endif