Revert "hw/386: Add EPYC mode topology decoding functions"
[qemu.git] / include / hw / i386 / topology.h
1 /*
2 * x86 CPU topology data structures and functions
3 *
4 * Copyright (c) 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef HW_I386_TOPOLOGY_H
25 #define HW_I386_TOPOLOGY_H
26
27 /* This file implements the APIC-ID-based CPU topology enumeration logic,
28 * documented at the following document:
29 * IntelĀ® 64 Architecture Processor Topology Enumeration
30 * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
31 *
32 * This code should be compatible with AMD's "Extended Method" described at:
33 * AMD CPUID Specification (Publication #25481)
34 * Section 3: Multiple Core Calcuation
35 * as long as:
36 * nr_threads is set to 1;
37 * OFFSET_IDX is assumed to be 0;
38 * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
39 */
40
41
42 #include "qemu/bitops.h"
43
44 /* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support
45 */
46 typedef uint32_t apic_id_t;
47
48 typedef struct X86CPUTopoIDs {
49 unsigned pkg_id;
50 unsigned die_id;
51 unsigned core_id;
52 unsigned smt_id;
53 } X86CPUTopoIDs;
54
55 typedef struct X86CPUTopoInfo {
56 unsigned nodes_per_pkg;
57 unsigned dies_per_pkg;
58 unsigned cores_per_die;
59 unsigned threads_per_core;
60 } X86CPUTopoInfo;
61
62 /* Return the bit width needed for 'count' IDs
63 */
64 static unsigned apicid_bitwidth_for_count(unsigned count)
65 {
66 g_assert(count >= 1);
67 count -= 1;
68 return count ? 32 - clz32(count) : 0;
69 }
70
71 /* Bit width of the SMT_ID (thread ID) field on the APIC ID
72 */
73 static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info)
74 {
75 return apicid_bitwidth_for_count(topo_info->threads_per_core);
76 }
77
78 /* Bit width of the Core_ID field
79 */
80 static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info)
81 {
82 return apicid_bitwidth_for_count(topo_info->cores_per_die);
83 }
84
85 /* Bit width of the Die_ID field */
86 static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info)
87 {
88 return apicid_bitwidth_for_count(topo_info->dies_per_pkg);
89 }
90
91 /* Bit offset of the Core_ID field
92 */
93 static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info)
94 {
95 return apicid_smt_width(topo_info);
96 }
97
98 /* Bit offset of the Die_ID field */
99 static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info)
100 {
101 return apicid_core_offset(topo_info) + apicid_core_width(topo_info);
102 }
103
104 /* Bit offset of the Pkg_ID (socket ID) field
105 */
106 static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info)
107 {
108 return apicid_die_offset(topo_info) + apicid_die_width(topo_info);
109 }
110
111 /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID
112 *
113 * The caller must make sure core_id < nr_cores and smt_id < nr_threads.
114 */
115 static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info,
116 const X86CPUTopoIDs *topo_ids)
117 {
118 return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) |
119 (topo_ids->die_id << apicid_die_offset(topo_info)) |
120 (topo_ids->core_id << apicid_core_offset(topo_info)) |
121 topo_ids->smt_id;
122 }
123
124 /* Calculate thread/core/package IDs for a specific topology,
125 * based on (contiguous) CPU index
126 */
127 static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info,
128 unsigned cpu_index,
129 X86CPUTopoIDs *topo_ids)
130 {
131 unsigned nr_dies = topo_info->dies_per_pkg;
132 unsigned nr_cores = topo_info->cores_per_die;
133 unsigned nr_threads = topo_info->threads_per_core;
134
135 topo_ids->pkg_id = cpu_index / (nr_dies * nr_cores * nr_threads);
136 topo_ids->die_id = cpu_index / (nr_cores * nr_threads) % nr_dies;
137 topo_ids->core_id = cpu_index / nr_threads % nr_cores;
138 topo_ids->smt_id = cpu_index % nr_threads;
139 }
140
141 /* Calculate thread/core/package IDs for a specific topology,
142 * based on APIC ID
143 */
144 static inline void x86_topo_ids_from_apicid(apic_id_t apicid,
145 X86CPUTopoInfo *topo_info,
146 X86CPUTopoIDs *topo_ids)
147 {
148 topo_ids->smt_id = apicid &
149 ~(0xFFFFFFFFUL << apicid_smt_width(topo_info));
150 topo_ids->core_id =
151 (apicid >> apicid_core_offset(topo_info)) &
152 ~(0xFFFFFFFFUL << apicid_core_width(topo_info));
153 topo_ids->die_id =
154 (apicid >> apicid_die_offset(topo_info)) &
155 ~(0xFFFFFFFFUL << apicid_die_width(topo_info));
156 topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info);
157 }
158
159 /* Make APIC ID for the CPU 'cpu_index'
160 *
161 * 'cpu_index' is a sequential, contiguous ID for the CPU.
162 */
163 static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
164 unsigned cpu_index)
165 {
166 X86CPUTopoIDs topo_ids;
167 x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids);
168 return x86_apicid_from_topo_ids(topo_info, &topo_ids);
169 }
170
171 #endif /* HW_I386_TOPOLOGY_H */