ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / i386 / x86-iommu.h
1 /*
2 * Common IOMMU interface for X86 platform
3 *
4 * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef HW_I386_X86_IOMMU_H
21 #define HW_I386_X86_IOMMU_H
22
23 #include "hw/sysbus.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26
27 #define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
28 #define X86_IOMMU_DEVICE(obj) \
29 OBJECT_CHECK(X86IOMMUState, (obj), TYPE_X86_IOMMU_DEVICE)
30 #define X86_IOMMU_DEVICE_CLASS(klass) \
31 OBJECT_CLASS_CHECK(X86IOMMUClass, (klass), TYPE_X86_IOMMU_DEVICE)
32 #define X86_IOMMU_DEVICE_GET_CLASS(obj) \
33 OBJECT_GET_CLASS(X86IOMMUClass, obj, TYPE_X86_IOMMU_DEVICE)
34
35 #define X86_IOMMU_SID_INVALID (0xffff)
36
37 typedef struct X86IOMMUState X86IOMMUState;
38 typedef struct X86IOMMUClass X86IOMMUClass;
39 typedef struct X86IOMMUIrq X86IOMMUIrq;
40 typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;
41
42 typedef enum IommuType {
43 TYPE_INTEL,
44 TYPE_AMD,
45 TYPE_NONE
46 } IommuType;
47
48 struct X86IOMMUClass {
49 SysBusDeviceClass parent;
50 /* Intel/AMD specific realize() hook */
51 DeviceRealize realize;
52 /* MSI-based interrupt remapping */
53 int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
54 MSIMessage *dst, uint16_t sid);
55 };
56
57 /**
58 * iec_notify_fn - IEC (Interrupt Entry Cache) notifier hook,
59 * triggered when IR invalidation happens.
60 * @private: private data
61 * @global: whether this is a global IEC invalidation
62 * @index: IRTE index to invalidate (start from)
63 * @mask: invalidation mask
64 */
65 typedef void (*iec_notify_fn)(void *private, bool global,
66 uint32_t index, uint32_t mask);
67
68 struct IEC_Notifier {
69 iec_notify_fn iec_notify;
70 void *private;
71 QLIST_ENTRY(IEC_Notifier) list;
72 };
73 typedef struct IEC_Notifier IEC_Notifier;
74
75 struct X86IOMMUState {
76 SysBusDevice busdev;
77 OnOffAuto intr_supported; /* Whether vIOMMU supports IR */
78 bool dt_supported; /* Whether vIOMMU supports DT */
79 bool pt_supported; /* Whether vIOMMU supports pass-through */
80 IommuType type; /* IOMMU type - AMD/Intel */
81 QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
82 };
83
84 bool x86_iommu_ir_supported(X86IOMMUState *s);
85
86 /* Generic IRQ entry information when interrupt remapping is enabled */
87 struct X86IOMMUIrq {
88 /* Used by both IOAPIC/MSI interrupt remapping */
89 uint8_t trigger_mode;
90 uint8_t vector;
91 uint8_t delivery_mode;
92 uint32_t dest;
93 uint8_t dest_mode;
94
95 /* only used by MSI interrupt remapping */
96 uint8_t redir_hint;
97 uint8_t msi_addr_last_bits;
98 };
99
100 struct X86IOMMU_MSIMessage {
101 union {
102 struct {
103 #ifdef HOST_WORDS_BIGENDIAN
104 uint32_t __addr_head:12; /* 0xfee */
105 uint32_t dest:8;
106 uint32_t __reserved:8;
107 uint32_t redir_hint:1;
108 uint32_t dest_mode:1;
109 uint32_t __not_used:2;
110 #else
111 uint32_t __not_used:2;
112 uint32_t dest_mode:1;
113 uint32_t redir_hint:1;
114 uint32_t __reserved:8;
115 uint32_t dest:8;
116 uint32_t __addr_head:12; /* 0xfee */
117 #endif
118 uint32_t __addr_hi;
119 } QEMU_PACKED;
120 uint64_t msi_addr;
121 };
122 union {
123 struct {
124 #ifdef HOST_WORDS_BIGENDIAN
125 uint16_t trigger_mode:1;
126 uint16_t level:1;
127 uint16_t __resved:3;
128 uint16_t delivery_mode:3;
129 uint16_t vector:8;
130 #else
131 uint16_t vector:8;
132 uint16_t delivery_mode:3;
133 uint16_t __resved:3;
134 uint16_t level:1;
135 uint16_t trigger_mode:1;
136 #endif
137 uint16_t __resved1;
138 } QEMU_PACKED;
139 uint32_t msi_data;
140 };
141 };
142
143 /**
144 * x86_iommu_get_default - get default IOMMU device
145 * @return: pointer to default IOMMU device
146 */
147 X86IOMMUState *x86_iommu_get_default(void);
148
149 /*
150 * x86_iommu_get_type - get IOMMU type
151 */
152 IommuType x86_iommu_get_type(void);
153
154 /**
155 * x86_iommu_iec_register_notifier - register IEC (Interrupt Entry
156 * Cache) notifiers
157 * @iommu: IOMMU device to register
158 * @fn: IEC notifier hook function
159 * @data: notifier private data
160 */
161 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
162 iec_notify_fn fn, void *data);
163
164 /**
165 * x86_iommu_iec_notify_all - Notify IEC invalidations
166 * @iommu: IOMMU device that sends the notification
167 * @global: whether this is a global invalidation. If true, @index
168 * and @mask are undefined.
169 * @index: starting index of interrupt entry to invalidate
170 * @mask: index mask for the invalidation
171 */
172 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
173 uint32_t index, uint32_t mask);
174
175 /**
176 * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq
177 * @X86IOMMUIrq: The IRQ information
178 * @out: Output MSI message
179 */
180 void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out);
181 #endif