Merge tag 'hppa-serial-fix-pull-request' of https://github.com/hdeller/qemu-hppa...
[qemu.git] / include / hw / i386 / x86.h
1 /*
2 * Copyright (c) 2019 Red Hat, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2 or later, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #ifndef HW_I386_X86_H
18 #define HW_I386_X86_H
19
20 #include "exec/hwaddr.h"
21 #include "qemu/notify.h"
22
23 #include "hw/i386/topology.h"
24 #include "hw/boards.h"
25 #include "hw/nmi.h"
26 #include "hw/isa/isa.h"
27 #include "hw/i386/ioapic.h"
28 #include "qom/object.h"
29
30 struct X86MachineClass {
31 /*< private >*/
32 MachineClass parent;
33
34 /*< public >*/
35
36 /* TSC rate migration: */
37 bool save_tsc_khz;
38 /* use DMA capable linuxboot option rom */
39 bool fwcfg_dma_enabled;
40 };
41
42 struct X86MachineState {
43 /*< private >*/
44 MachineState parent;
45
46 /*< public >*/
47
48 /* Pointers to devices and objects: */
49 ISADevice *rtc;
50 FWCfgState *fw_cfg;
51 qemu_irq *gsi;
52 DeviceState *ioapic2;
53 GMappedFile *initrd_mapped_file;
54 HotplugHandler *acpi_dev;
55
56 /* RAM information (sizes, addresses, configuration): */
57 ram_addr_t below_4g_mem_size, above_4g_mem_size;
58
59 /* CPU and apic information: */
60 bool apic_xrupt_override;
61 unsigned pci_irq_mask;
62 unsigned apic_id_limit;
63 uint16_t boot_cpus;
64 SgxEPCList *sgx_epc_list;
65
66 OnOffAuto smm;
67 OnOffAuto acpi;
68 OnOffAuto pit;
69 OnOffAuto pic;
70
71 char *oem_id;
72 char *oem_table_id;
73 /*
74 * Address space used by IOAPIC device. All IOAPIC interrupts
75 * will be translated to MSI messages in the address space.
76 */
77 AddressSpace *ioapic_as;
78
79 /*
80 * Ratelimit enforced on detected bus locks in guest.
81 * The default value of the bus_lock_ratelimit is 0 per second,
82 * which means no limitation on the guest's bus locks.
83 */
84 uint64_t bus_lock_ratelimit;
85 };
86
87 #define X86_MACHINE_SMM "smm"
88 #define X86_MACHINE_ACPI "acpi"
89 #define X86_MACHINE_PIT "pit"
90 #define X86_MACHINE_PIC "pic"
91 #define X86_MACHINE_OEM_ID "x-oem-id"
92 #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id"
93 #define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit"
94
95 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86")
96 OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
97
98 void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
99
100 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
101 unsigned int cpu_index);
102
103 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
104 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
105 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
106 unsigned cpu_index);
107 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
108 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
109 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx);
110 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count);
111 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
112 DeviceState *dev, Error **errp);
113 void x86_cpu_plug(HotplugHandler *hotplug_dev,
114 DeviceState *dev, Error **errp);
115 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
116 DeviceState *dev, Error **errp);
117 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
118 DeviceState *dev, Error **errp);
119
120 void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
121 MemoryRegion *rom_memory, bool isapc_ram_fw);
122
123 void x86_load_linux(X86MachineState *x86ms,
124 FWCfgState *fw_cfg,
125 int acpi_data_size,
126 bool pvh_enabled);
127
128 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms);
129 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
130
131 /* Global System Interrupts */
132
133 #define GSI_NUM_PINS IOAPIC_NUM_PINS
134 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
135
136 typedef struct GSIState {
137 qemu_irq i8259_irq[ISA_NUM_IRQS];
138 qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
139 qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
140 } GSIState;
141
142 qemu_irq x86_allocate_cpu_irq(void);
143 void gsi_handler(void *opaque, int n, int level);
144 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
145 DeviceState *ioapic_init_secondary(GSIState *gsi_state);
146
147 /* pc_sysfw.c */
148 void x86_firmware_configure(void *ptr, int size);
149
150 #endif