ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / intc / bcm2836_control.h
1 /*
2 * Raspberry Pi emulation (c) 2012 Gregory Estrade
3 * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
4 *
5 * Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
6 * Written by Andrew Baumann
7 *
8 * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
9 * Added basic IRQ_TIMER interrupt support
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 */
14
15 #ifndef BCM2836_CONTROL_H
16 #define BCM2836_CONTROL_H
17
18 #include "hw/sysbus.h"
19 #include "qemu/timer.h"
20
21 /* 4 mailboxes per core, for 16 total */
22 #define BCM2836_NCORES 4
23 #define BCM2836_MBPERCORE 4
24
25 #define TYPE_BCM2836_CONTROL "bcm2836-control"
26 #define BCM2836_CONTROL(obj) \
27 OBJECT_CHECK(BCM2836ControlState, (obj), TYPE_BCM2836_CONTROL)
28
29 typedef struct BCM2836ControlState {
30 /*< private >*/
31 SysBusDevice busdev;
32 /*< public >*/
33 MemoryRegion iomem;
34
35 /* mailbox state */
36 uint32_t mailboxes[BCM2836_NCORES * BCM2836_MBPERCORE];
37
38 /* interrupt routing/control registers */
39 uint8_t route_gpu_irq, route_gpu_fiq;
40 uint32_t timercontrol[BCM2836_NCORES];
41 uint32_t mailboxcontrol[BCM2836_NCORES];
42
43 /* interrupt status regs (derived from input pins; not visible to user) */
44 bool gpu_irq, gpu_fiq;
45 uint8_t timerirqs[BCM2836_NCORES];
46
47 /* local timer */
48 QEMUTimer timer;
49 uint32_t local_timer_control;
50 uint8_t route_localtimer;
51
52 /* interrupt source registers, post-routing (also input-derived; visible) */
53 uint32_t irqsrc[BCM2836_NCORES];
54 uint32_t fiqsrc[BCM2836_NCORES];
55
56 /* outputs to CPU cores */
57 qemu_irq irq[BCM2836_NCORES];
58 qemu_irq fiq[BCM2836_NCORES];
59 } BCM2836ControlState;
60
61 #endif