ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / misc / aspeed_scu.h
1 /*
2 * ASPEED System Control Unit
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11 #ifndef ASPEED_SCU_H
12 #define ASPEED_SCU_H
13
14 #include "hw/sysbus.h"
15
16 #define TYPE_ASPEED_SCU "aspeed.scu"
17 #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU)
18 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
19 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
20 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
21
22 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
23 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
24
25 typedef struct AspeedSCUState {
26 /*< private >*/
27 SysBusDevice parent_obj;
28
29 /*< public >*/
30 MemoryRegion iomem;
31
32 uint32_t regs[ASPEED_AST2600_SCU_NR_REGS];
33 uint32_t silicon_rev;
34 uint32_t hw_strap1;
35 uint32_t hw_strap2;
36 uint32_t hw_prot_key;
37 } AspeedSCUState;
38
39 #define AST2400_A0_SILICON_REV 0x02000303U
40 #define AST2400_A1_SILICON_REV 0x02010303U
41 #define AST2500_A0_SILICON_REV 0x04000303U
42 #define AST2500_A1_SILICON_REV 0x04010303U
43 #define AST2600_A0_SILICON_REV 0x05000303U
44 #define AST2600_A1_SILICON_REV 0x05010303U
45
46 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
47
48 extern bool is_supported_silicon_rev(uint32_t silicon_rev);
49
50 #define ASPEED_SCU_CLASS(klass) \
51 OBJECT_CLASS_CHECK(AspeedSCUClass, (klass), TYPE_ASPEED_SCU)
52 #define ASPEED_SCU_GET_CLASS(obj) \
53 OBJECT_GET_CLASS(AspeedSCUClass, (obj), TYPE_ASPEED_SCU)
54
55 typedef struct AspeedSCUClass {
56 SysBusDeviceClass parent_class;
57
58 const uint32_t *resets;
59 uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg);
60 uint32_t apb_divider;
61 uint32_t nr_regs;
62 const MemoryRegionOps *ops;
63 } AspeedSCUClass;
64
65 #define ASPEED_SCU_PROT_KEY 0x1688A8A8
66
67 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s);
68
69 /*
70 * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
71 * were added.
72 *
73 * Original header file :
74 * arch/arm/mach-aspeed/include/mach/regs-scu.h
75 *
76 * Copyright (C) 2012-2020 ASPEED Technology Inc.
77 *
78 * This program is free software; you can redistribute it and/or modify
79 * it under the terms of the GNU General Public License version 2 as
80 * published by the Free Software Foundation.
81 *
82 * History :
83 * 1. 2012/12/29 Ryan Chen Create
84 */
85
86 /* SCU08 Clock Selection Register
87 *
88 * 31 Enable Video Engine clock dynamic slow down
89 * 30:28 Video Engine clock slow down setting
90 * 27 2D Engine GCLK clock source selection
91 * 26 2D Engine GCLK clock throttling enable
92 * 25:23 APB PCLK divider selection
93 * 22:20 LPC Host LHCLK divider selection
94 * 19 LPC Host LHCLK clock generation/output enable control
95 * 18:16 MAC AHB bus clock divider selection
96 * 15 SD/SDIO clock running enable
97 * 14:12 SD/SDIO divider selection
98 * 11 Reserved
99 * 10:8 Video port output clock delay control bit
100 * 7 ARM CPU/AHB clock slow down enable
101 * 6:4 ARM CPU/AHB clock slow down setting
102 * 3:2 ECLK clock source selection
103 * 1 CPU/AHB clock slow down idle timer
104 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
105 */
106 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
107
108 /* SCU24 H-PLL Parameter Register (for Aspeed AST2400 SOC)
109 *
110 * 18 H-PLL parameter selection
111 * 0: Select H-PLL by strapping resistors
112 * 1: Select H-PLL by the programmed registers (SCU24[17:0])
113 * 17 Enable H-PLL bypass mode
114 * 16 Turn off H-PLL
115 * 10:5 H-PLL Numerator
116 * 4 H-PLL Output Divider
117 * 3:0 H-PLL Denumerator
118 *
119 * (Output frequency) = 24MHz * (2-OD) * [(Numerator+2) / (Denumerator+1)]
120 */
121
122 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
123 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
124 #define SCU_AST2400_H_PLL_OFF (0x1 << 16)
125
126 /* SCU24 H-PLL Parameter Register (for Aspeed AST2500 SOC)
127 *
128 * 21 Enable H-PLL reset
129 * 20 Enable H-PLL bypass mode
130 * 19 Turn off H-PLL
131 * 18:13 H-PLL Post Divider
132 * 12:5 H-PLL Numerator (M)
133 * 4:0 H-PLL Denumerator (N)
134 *
135 * (Output frequency) = CLKIN(24MHz) * [(M+1) / (N+1)] / (P+1)
136 *
137 * The default frequency is 792Mhz when CLKIN = 24MHz
138 */
139
140 #define SCU_H_PLL_BYPASS_EN (0x1 << 20)
141 #define SCU_H_PLL_OFF (0x1 << 19)
142
143 /* SCU70 Hardware Strapping Register definition (for Aspeed AST2400 SOC)
144 *
145 * 31:29 Software defined strapping registers
146 * 28:27 DRAM size setting (for VGA driver use)
147 * 26:24 DRAM configuration setting
148 * 23 Enable 25 MHz reference clock input
149 * 22 Enable GPIOE pass-through mode
150 * 21 Enable GPIOD pass-through mode
151 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
152 * 19 Disable ACPI function
153 * 23,18 Clock source selection
154 * 17 Enable BMC 2nd boot watchdog timer
155 * 16 SuperIO configuration address selection
156 * 15 VGA Class Code selection
157 * 14 Enable LPC dedicated reset pin function
158 * 13:12 SPI mode selection
159 * 11:10 CPU/AHB clock frequency ratio selection
160 * 9:8 H-PLL default clock frequency selection
161 * 7 Define MAC#2 interface
162 * 6 Define MAC#1 interface
163 * 5 Enable VGA BIOS ROM
164 * 4 Boot flash memory extended option
165 * 3:2 VGA memory size selection
166 * 1:0 BMC CPU boot code selection
167 */
168 #define SCU_AST2400_HW_STRAP_SW_DEFINE(x) ((x) << 29)
169 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29)
170
171 #define SCU_AST2400_HW_STRAP_DRAM_SIZE(x) ((x) << 27)
172 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
173 #define DRAM_SIZE_64MB 0
174 #define DRAM_SIZE_128MB 1
175 #define DRAM_SIZE_256MB 2
176 #define DRAM_SIZE_512MB 3
177
178 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG(x) ((x) << 24)
179 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
180
181 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
182 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
183 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
184 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19)
185
186 /* bit 23, 18 [1,0] */
187 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \
188 | (((x) & 0x1) << 18))
189 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
190 | (((x) >> 18) & 0x1))
191 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
192 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
193 #define AST2400_CLK_24M_IN 0
194 #define AST2400_CLK_48M_IN 1
195 #define AST2400_CLK_25M_IN_24M_USB_CKI 2
196 #define AST2400_CLK_25M_IN_48M_USB_CKI 3
197
198 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
199 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
200 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
201 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
202 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14)
203
204 #define SCU_HW_STRAP_SPI_MODE(x) ((x) << 12)
205 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12)
206 #define SCU_HW_STRAP_SPI_DIS 0
207 #define SCU_HW_STRAP_SPI_MASTER 1
208 #define SCU_HW_STRAP_SPI_M_S_EN 2
209 #define SCU_HW_STRAP_SPI_PASS_THROUGH 3
210
211 #define SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(x) ((x) << 10)
212 #define SCU_AST2400_HW_STRAP_GET_CPU_AHB_RATIO(x) (((x) >> 10) & 3)
213 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10)
214 #define AST2400_CPU_AHB_RATIO_1_1 0
215 #define AST2400_CPU_AHB_RATIO_2_1 1
216 #define AST2400_CPU_AHB_RATIO_4_1 2
217 #define AST2400_CPU_AHB_RATIO_3_1 3
218
219 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3)
220 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8)
221 #define AST2400_CPU_384MHZ 0
222 #define AST2400_CPU_360MHZ 1
223 #define AST2400_CPU_336MHZ 2
224 #define AST2400_CPU_408MHZ 3
225
226 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7)
227 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6)
228 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5)
229 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4)
230
231 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3)
232 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2)
233 #define SCU_HW_STRAP_VGA_SIZE_SET(x) ((x) << 2)
234 #define VGA_8M_DRAM 0
235 #define VGA_16M_DRAM 1
236 #define VGA_32M_DRAM 2
237 #define VGA_64M_DRAM 3
238
239 #define SCU_AST2400_HW_STRAP_BOOT_MODE(x) (x)
240 #define AST2400_NOR_BOOT 0
241 #define AST2400_NAND_BOOT 1
242 #define AST2400_SPI_BOOT 2
243 #define AST2400_DIS_BOOT 3
244
245 /*
246 * SCU70 Hardware strapping register definition (for Aspeed AST2500
247 * SoC and higher)
248 *
249 * 31 Enable SPI Flash Strap Auto Fetch Mode
250 * 30 Enable GPIO Strap Mode
251 * 29 Select UART Debug Port
252 * 28 Reserved (1)
253 * 27 Enable fast reset mode for ARM ICE debugger
254 * 26 Enable eSPI flash mode
255 * 25 Enable eSPI mode
256 * 24 Select DDR4 SDRAM
257 * 23 Select 25 MHz reference clock input mode
258 * 22 Enable GPIOE pass-through mode
259 * 21 Enable GPIOD pass-through mode
260 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
261 * 19 Enable ACPI function
262 * 18 Select USBCKI input frequency
263 * 17 Enable BMC 2nd boot watchdog timer
264 * 16 SuperIO configuration address selection
265 * 15 VGA Class Code selection
266 * 14 Select dedicated LPC reset input
267 * 13:12 SPI mode selection
268 * 11:9 AXI/AHB clock frequency ratio selection
269 * 8 Reserved (0)
270 * 7 Define MAC#2 interface
271 * 6 Define MAC#1 interface
272 * 5 Enable dedicated VGA BIOS ROM
273 * 4 Reserved (0)
274 * 3:2 VGA memory size selection
275 * 1 Reserved (1)
276 * 0 Disable CPU boot
277 */
278 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31)
279 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30)
280 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29)
281 #define UART_DEBUG_UART1 0
282 #define UART_DEBUG_UART5 1
283 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28)
284
285 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27)
286 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
287 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)
288 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)
289 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23)
290
291 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19)
292 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18)
293 #define USBCKI_FREQ_24MHZ 0
294 #define USBCKI_FREQ_28MHZ 1
295
296 #define SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(x) ((x) << 9)
297 #define SCU_AST2500_HW_STRAP_GET_AXI_AHB_RATIO(x) (((x) >> 9) & 7)
298 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9)
299 #define AXI_AHB_RATIO_UNDEFINED 0
300 #define AXI_AHB_RATIO_2_1 1
301 #define AXI_AHB_RATIO_3_1 2
302 #define AXI_AHB_RATIO_4_1 3
303 #define AXI_AHB_RATIO_5_1 4
304 #define AXI_AHB_RATIO_6_1 5
305 #define AXI_AHB_RATIO_7_1 6
306 #define AXI_AHB_RATIO_8_1 7
307
308 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1)
309 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0)
310
311 #define AST2500_HW_STRAP1_DEFAULTS ( \
312 SCU_AST2500_HW_STRAP_RESERVED28 | \
313 SCU_HW_STRAP_2ND_BOOT_WDT | \
314 SCU_HW_STRAP_VGA_CLASS_CODE | \
315 SCU_HW_STRAP_LPC_RESET_PIN | \
316 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
317 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
318 SCU_AST2500_HW_STRAP_RESERVED1)
319
320 #endif /* ASPEED_SCU_H */