ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / misc / aspeed_sdmc.h
1 /*
2 * ASPEED SDRAM Memory Controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9 #ifndef ASPEED_SDMC_H
10 #define ASPEED_SDMC_H
11
12 #include "hw/sysbus.h"
13
14 #define TYPE_ASPEED_SDMC "aspeed.sdmc"
15 #define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
16 #define TYPE_ASPEED_2400_SDMC TYPE_ASPEED_SDMC "-ast2400"
17 #define TYPE_ASPEED_2500_SDMC TYPE_ASPEED_SDMC "-ast2500"
18 #define TYPE_ASPEED_2600_SDMC TYPE_ASPEED_SDMC "-ast2600"
19
20 /*
21 * SDMC has 174 documented registers. In addition the u-boot device tree
22 * describes the following regions:
23 * - PHY status regs at offset 0x400, length 0x200
24 * - PHY setting regs at offset 0x100, length 0x300
25 *
26 * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
27 * system: one is in the SDRAM MC (memory controller) which is used in run
28 * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
29 * training.
30 */
31 #define ASPEED_SDMC_NR_REGS (0x500 >> 2)
32
33 typedef struct AspeedSDMCState {
34 /*< private >*/
35 SysBusDevice parent_obj;
36
37 /*< public >*/
38 MemoryRegion iomem;
39
40 uint32_t regs[ASPEED_SDMC_NR_REGS];
41 uint64_t ram_size;
42 uint64_t max_ram_size;
43 } AspeedSDMCState;
44
45 #define ASPEED_SDMC_CLASS(klass) \
46 OBJECT_CLASS_CHECK(AspeedSDMCClass, (klass), TYPE_ASPEED_SDMC)
47 #define ASPEED_SDMC_GET_CLASS(obj) \
48 OBJECT_GET_CLASS(AspeedSDMCClass, (obj), TYPE_ASPEED_SDMC)
49
50 typedef struct AspeedSDMCClass {
51 SysBusDeviceClass parent_class;
52
53 uint64_t max_ram_size;
54 const uint64_t *valid_ram_sizes;
55 uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data);
56 void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data);
57 } AspeedSDMCClass;
58
59 #endif /* ASPEED_SDMC_H */