ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / misc / mos6522.h
1 /*
2 * QEMU MOS6522 VIA emulation
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2018 Mark Cave-Ayland
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #ifndef MOS6522_H
28 #define MOS6522_H
29
30 #include "exec/memory.h"
31 #include "hw/sysbus.h"
32 #include "hw/input/adb.h"
33
34 /* Bits in ACR */
35 #define SR_CTRL 0x1c /* Shift register control bits */
36 #define SR_EXT 0x0c /* Shift on external clock */
37 #define SR_OUT 0x10 /* Shift out if 1 */
38
39 /* Bits in IFR and IER */
40 #define IER_SET 0x80 /* set bits in IER */
41 #define IER_CLR 0 /* clear bits in IER */
42
43 #define CA2_INT 0x01
44 #define CA1_INT 0x02
45 #define SR_INT 0x04 /* Shift register full/empty */
46 #define CB2_INT 0x08
47 #define CB1_INT 0x10
48 #define T2_INT 0x20 /* Timer 2 interrupt */
49 #define T1_INT 0x40 /* Timer 1 interrupt */
50
51 /* Bits in ACR */
52 #define T1MODE 0xc0 /* Timer 1 mode */
53 #define T1MODE_CONT 0x40 /* continuous interrupts */
54
55 /* VIA registers */
56 #define VIA_REG_B 0x00
57 #define VIA_REG_A 0x01
58 #define VIA_REG_DIRB 0x02
59 #define VIA_REG_DIRA 0x03
60 #define VIA_REG_T1CL 0x04
61 #define VIA_REG_T1CH 0x05
62 #define VIA_REG_T1LL 0x06
63 #define VIA_REG_T1LH 0x07
64 #define VIA_REG_T2CL 0x08
65 #define VIA_REG_T2CH 0x09
66 #define VIA_REG_SR 0x0a
67 #define VIA_REG_ACR 0x0b
68 #define VIA_REG_PCR 0x0c
69 #define VIA_REG_IFR 0x0d
70 #define VIA_REG_IER 0x0e
71 #define VIA_REG_ANH 0x0f
72
73 /**
74 * MOS6522Timer:
75 * @counter_value: counter value at load time
76 */
77 typedef struct MOS6522Timer {
78 int index;
79 uint16_t latch;
80 uint16_t counter_value;
81 int64_t load_time;
82 int64_t next_irq_time;
83 uint64_t frequency;
84 QEMUTimer *timer;
85 } MOS6522Timer;
86
87 /**
88 * MOS6522State:
89 * @b: B-side data
90 * @a: A-side data
91 * @dirb: B-side direction (1=output)
92 * @dira: A-side direction (1=output)
93 * @sr: Shift register
94 * @acr: Auxiliary control register
95 * @pcr: Peripheral control register
96 * @ifr: Interrupt flag register
97 * @ier: Interrupt enable register
98 * @anh: A-side data, no handshake
99 * @last_b: last value of B register
100 * @last_acr: last value of ACR register
101 */
102 typedef struct MOS6522State {
103 /*< private >*/
104 SysBusDevice parent_obj;
105 /*< public >*/
106
107 MemoryRegion mem;
108 /* VIA registers */
109 uint8_t b;
110 uint8_t a;
111 uint8_t dirb;
112 uint8_t dira;
113 uint8_t sr;
114 uint8_t acr;
115 uint8_t pcr;
116 uint8_t ifr;
117 uint8_t ier;
118
119 MOS6522Timer timers[2];
120 uint64_t frequency;
121
122 qemu_irq irq;
123 } MOS6522State;
124
125 #define TYPE_MOS6522 "mos6522"
126 #define MOS6522(obj) OBJECT_CHECK(MOS6522State, (obj), TYPE_MOS6522)
127
128 typedef struct MOS6522DeviceClass {
129 DeviceClass parent_class;
130
131 DeviceReset parent_reset;
132 void (*set_sr_int)(MOS6522State *dev);
133 void (*portB_write)(MOS6522State *dev);
134 void (*portA_write)(MOS6522State *dev);
135 void (*update_irq)(MOS6522State *dev);
136 /* These are used to influence the CUDA MacOS timebase calibration */
137 uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
138 uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
139 uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
140 uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
141 } MOS6522DeviceClass;
142
143 #define MOS6522_CLASS(cls) \
144 OBJECT_CLASS_CHECK(MOS6522DeviceClass, (cls), TYPE_MOS6522)
145 #define MOS6522_GET_CLASS(obj) \
146 OBJECT_GET_CLASS(MOS6522DeviceClass, (obj), TYPE_MOS6522)
147
148 extern const VMStateDescription vmstate_mos6522;
149
150 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
151 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
152
153 #endif /* MOS6522_H */