Merge tag 'pull-for-6.2-291121-1' of https://github.com/stsquad/qemu into staging
[qemu.git] / include / hw / misc / sifive_u_prci.h
1 /*
2 * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface
3 *
4 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #ifndef HW_SIFIVE_U_PRCI_H
20 #define HW_SIFIVE_U_PRCI_H
21 #include "qom/object.h"
22
23 #define SIFIVE_U_PRCI_HFXOSCCFG 0x00
24 #define SIFIVE_U_PRCI_COREPLLCFG0 0x04
25 #define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C
26 #define SIFIVE_U_PRCI_DDRPLLCFG1 0x10
27 #define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C
28 #define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20
29 #define SIFIVE_U_PRCI_CORECLKSEL 0x24
30 #define SIFIVE_U_PRCI_DEVICESRESET 0x28
31 #define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C
32
33 /*
34 * Current FU540-C000 manual says ready bit is at bit 29, but
35 * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
36 * We have to trust the actual code that works.
37 *
38 * see https://github.com/sifive/freedom-u540-c000-bootloader
39 */
40
41 #define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30)
42 #define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31)
43
44 /* xxxPLLCFG0 register bits */
45 #define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0)
46 #define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6)
47 #define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15)
48 #define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25)
49 #define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31)
50
51 /* xxxPLLCFG1 register bits */
52 #define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24)
53
54 /* coreclksel register bits */
55 #define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0)
56
57
58 #define SIFIVE_U_PRCI_REG_SIZE 0x1000
59
60 #define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci"
61
62 typedef struct SiFiveUPRCIState SiFiveUPRCIState;
63 DECLARE_INSTANCE_CHECKER(SiFiveUPRCIState, SIFIVE_U_PRCI,
64 TYPE_SIFIVE_U_PRCI)
65
66 struct SiFiveUPRCIState {
67 /*< private >*/
68 SysBusDevice parent_obj;
69
70 /*< public >*/
71 MemoryRegion mmio;
72 uint32_t hfxosccfg;
73 uint32_t corepllcfg0;
74 uint32_t ddrpllcfg0;
75 uint32_t ddrpllcfg1;
76 uint32_t gemgxlpllcfg0;
77 uint32_t gemgxlpllcfg1;
78 uint32_t coreclksel;
79 uint32_t devicesreset;
80 uint32_t clkmuxstatus;
81 };
82
83 /*
84 * Clock indexes for use by Device Tree data and the PRCI driver.
85 *
86 * These values are from sifive-fu540-prci.h in the Linux kernel.
87 */
88 #define PRCI_CLK_COREPLL 0
89 #define PRCI_CLK_DDRPLL 1
90 #define PRCI_CLK_GEMGXLPLL 2
91 #define PRCI_CLK_TLCLK 3
92
93 #endif /* HW_SIFIVE_U_PRCI_H */