ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / net / allwinner-sun8i-emac.h
1 /*
2 * Allwinner Sun8i Ethernet MAC emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
21 #define HW_NET_ALLWINNER_SUN8I_EMAC_H
22
23 #include "qom/object.h"
24 #include "net/net.h"
25 #include "hw/sysbus.h"
26
27 /**
28 * Object model
29 * @{
30 */
31
32 #define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
33 #define AW_SUN8I_EMAC(obj) \
34 OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
35
36 /** @} */
37
38 /**
39 * Allwinner Sun8i EMAC object instance state
40 */
41 typedef struct AwSun8iEmacState {
42 /*< private >*/
43 SysBusDevice parent_obj;
44 /*< public >*/
45
46 /** Maps I/O registers in physical memory */
47 MemoryRegion iomem;
48
49 /** Interrupt output signal to notify CPU */
50 qemu_irq irq;
51
52 /** Memory region where DMA transfers are done */
53 MemoryRegion *dma_mr;
54
55 /** Address space used internally for DMA transfers */
56 AddressSpace dma_as;
57
58 /** Generic Network Interface Controller (NIC) for networking API */
59 NICState *nic;
60
61 /** Generic Network Interface Controller (NIC) configuration */
62 NICConf conf;
63
64 /**
65 * @name Media Independent Interface (MII)
66 * @{
67 */
68
69 uint8_t mii_phy_addr; /**< PHY address */
70 uint32_t mii_cr; /**< Control */
71 uint32_t mii_st; /**< Status */
72 uint32_t mii_adv; /**< Advertised Abilities */
73
74 /** @} */
75
76 /**
77 * @name Hardware Registers
78 * @{
79 */
80
81 uint32_t basic_ctl0; /**< Basic Control 0 */
82 uint32_t basic_ctl1; /**< Basic Control 1 */
83 uint32_t int_en; /**< Interrupt Enable */
84 uint32_t int_sta; /**< Interrupt Status */
85 uint32_t frm_flt; /**< Receive Frame Filter */
86
87 uint32_t rx_ctl0; /**< Receive Control 0 */
88 uint32_t rx_ctl1; /**< Receive Control 1 */
89 uint32_t rx_desc_head; /**< Receive Descriptor List Address */
90 uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
91
92 uint32_t tx_ctl0; /**< Transmit Control 0 */
93 uint32_t tx_ctl1; /**< Transmit Control 1 */
94 uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
95 uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
96 uint32_t tx_flowctl; /**< Transmit Flow Control */
97
98 uint32_t mii_cmd; /**< Management Interface Command */
99 uint32_t mii_data; /**< Management Interface Data */
100
101 /** @} */
102
103 } AwSun8iEmacState;
104
105 #endif /* HW_NET_ALLWINNER_SUN8I_H */