ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / net / allwinner_emac.h
1 /*
2 * Emulation of Allwinner EMAC Fast Ethernet controller and
3 * Realtek RTL8201CP PHY
4 *
5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6 *
7 * Allwinner EMAC register definitions from Linux kernel are:
8 * Copyright 2012 Stefan Roese <sr@denx.de>
9 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
10 * Copyright 1997 Sten Wang
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22
23 #ifndef ALLWINNER_EMAC_H
24 #define ALLWINNER_EMAC_H
25
26 #include "qemu/units.h"
27 #include "net/net.h"
28 #include "qemu/fifo8.h"
29 #include "hw/net/mii.h"
30 #include "hw/sysbus.h"
31
32 #define TYPE_AW_EMAC "allwinner-emac"
33 #define AW_EMAC(obj) OBJECT_CHECK(AwEmacState, (obj), TYPE_AW_EMAC)
34
35 /*
36 * Allwinner EMAC register list
37 */
38 #define EMAC_CTL_REG 0x00
39
40 #define EMAC_TX_MODE_REG 0x04
41 #define EMAC_TX_FLOW_REG 0x08
42 #define EMAC_TX_CTL0_REG 0x0C
43 #define EMAC_TX_CTL1_REG 0x10
44 #define EMAC_TX_INS_REG 0x14
45 #define EMAC_TX_PL0_REG 0x18
46 #define EMAC_TX_PL1_REG 0x1C
47 #define EMAC_TX_STA_REG 0x20
48 #define EMAC_TX_IO_DATA_REG 0x24
49 #define EMAC_TX_IO_DATA1_REG 0x28
50 #define EMAC_TX_TSVL0_REG 0x2C
51 #define EMAC_TX_TSVH0_REG 0x30
52 #define EMAC_TX_TSVL1_REG 0x34
53 #define EMAC_TX_TSVH1_REG 0x38
54
55 #define EMAC_RX_CTL_REG 0x3C
56 #define EMAC_RX_HASH0_REG 0x40
57 #define EMAC_RX_HASH1_REG 0x44
58 #define EMAC_RX_STA_REG 0x48
59 #define EMAC_RX_IO_DATA_REG 0x4C
60 #define EMAC_RX_FBC_REG 0x50
61
62 #define EMAC_INT_CTL_REG 0x54
63 #define EMAC_INT_STA_REG 0x58
64
65 #define EMAC_MAC_CTL0_REG 0x5C
66 #define EMAC_MAC_CTL1_REG 0x60
67 #define EMAC_MAC_IPGT_REG 0x64
68 #define EMAC_MAC_IPGR_REG 0x68
69 #define EMAC_MAC_CLRT_REG 0x6C
70 #define EMAC_MAC_MAXF_REG 0x70
71 #define EMAC_MAC_SUPP_REG 0x74
72 #define EMAC_MAC_TEST_REG 0x78
73 #define EMAC_MAC_MCFG_REG 0x7C
74 #define EMAC_MAC_MCMD_REG 0x80
75 #define EMAC_MAC_MADR_REG 0x84
76 #define EMAC_MAC_MWTD_REG 0x88
77 #define EMAC_MAC_MRDD_REG 0x8C
78 #define EMAC_MAC_MIND_REG 0x90
79 #define EMAC_MAC_SSRR_REG 0x94
80 #define EMAC_MAC_A0_REG 0x98
81 #define EMAC_MAC_A1_REG 0x9C
82 #define EMAC_MAC_A2_REG 0xA0
83
84 #define EMAC_SAFX_L_REG0 0xA4
85 #define EMAC_SAFX_H_REG0 0xA8
86 #define EMAC_SAFX_L_REG1 0xAC
87 #define EMAC_SAFX_H_REG1 0xB0
88 #define EMAC_SAFX_L_REG2 0xB4
89 #define EMAC_SAFX_H_REG2 0xB8
90 #define EMAC_SAFX_L_REG3 0xBC
91 #define EMAC_SAFX_H_REG3 0xC0
92
93 /* CTL register fields */
94 #define EMAC_CTL_RESET (1 << 0)
95 #define EMAC_CTL_TX_EN (1 << 1)
96 #define EMAC_CTL_RX_EN (1 << 2)
97
98 /* TX MODE register fields */
99 #define EMAC_TX_MODE_ABORTED_FRAME_EN (1 << 0)
100 #define EMAC_TX_MODE_DMA_EN (1 << 1)
101
102 /* RX CTL register fields */
103 #define EMAC_RX_CTL_AUTO_DRQ_EN (1 << 1)
104 #define EMAC_RX_CTL_DMA_EN (1 << 2)
105 #define EMAC_RX_CTL_PASS_ALL_EN (1 << 4)
106 #define EMAC_RX_CTL_PASS_CTL_EN (1 << 5)
107 #define EMAC_RX_CTL_PASS_CRC_ERR_EN (1 << 6)
108 #define EMAC_RX_CTL_PASS_LEN_ERR_EN (1 << 7)
109 #define EMAC_RX_CTL_PASS_LEN_OOR_EN (1 << 8)
110 #define EMAC_RX_CTL_ACCEPT_UNICAST_EN (1 << 16)
111 #define EMAC_RX_CTL_DA_FILTER_EN (1 << 17)
112 #define EMAC_RX_CTL_ACCEPT_MULTICAST_EN (1 << 20)
113 #define EMAC_RX_CTL_HASH_FILTER_EN (1 << 21)
114 #define EMAC_RX_CTL_ACCEPT_BROADCAST_EN (1 << 22)
115 #define EMAC_RX_CTL_SA_FILTER_EN (1 << 24)
116 #define EMAC_RX_CTL_SA_FILTER_INVERT_EN (1 << 25)
117
118 /* RX IO DATA register fields */
119 #define EMAC_RX_HEADER(len, status) (((len) & 0xffff) | ((status) << 16))
120 #define EMAC_RX_IO_DATA_STATUS_CRC_ERR (1 << 4)
121 #define EMAC_RX_IO_DATA_STATUS_LEN_ERR (3 << 5)
122 #define EMAC_RX_IO_DATA_STATUS_OK (1 << 7)
123 #define EMAC_UNDOCUMENTED_MAGIC 0x0143414d /* header for RX frames */
124
125 /* INT CTL and INT STA registers fields */
126 #define EMAC_INT_TX_CHAN(x) (1 << (x))
127 #define EMAC_INT_RX (1 << 8)
128
129 /* Due to lack of specifications, size of fifos is chosen arbitrarily */
130 #define TX_FIFO_SIZE (4 * KiB)
131 #define RX_FIFO_SIZE (32 * KiB)
132
133 #define NUM_TX_FIFOS 2
134 #define RX_HDR_SIZE 8
135 #define CRC_SIZE 4
136
137 #define PHY_REG_SHIFT 0
138 #define PHY_ADDR_SHIFT 8
139
140 typedef struct RTL8201CPState {
141 uint16_t bmcr;
142 uint16_t bmsr;
143 uint16_t anar;
144 uint16_t anlpar;
145 } RTL8201CPState;
146
147 typedef struct AwEmacState {
148 /*< private >*/
149 SysBusDevice parent_obj;
150 /*< public >*/
151
152 MemoryRegion iomem;
153 qemu_irq irq;
154 NICState *nic;
155 NICConf conf;
156 RTL8201CPState mii;
157 uint8_t phy_addr;
158
159 uint32_t ctl;
160 uint32_t tx_mode;
161 uint32_t rx_ctl;
162 uint32_t int_ctl;
163 uint32_t int_sta;
164 uint32_t phy_target;
165
166 Fifo8 rx_fifo;
167 uint32_t rx_num_packets;
168 uint32_t rx_packet_size;
169 uint32_t rx_packet_pos;
170
171 Fifo8 tx_fifo[NUM_TX_FIFOS];
172 uint32_t tx_length[NUM_TX_FIFOS];
173 uint32_t tx_channel;
174 } AwEmacState;
175
176 #endif