ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / net / cadence_gem.h
1 /*
2 * QEMU Cadence GEM emulation
3 *
4 * Copyright (c) 2011 Xilinx, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef CADENCE_GEM_H
26 #define CADENCE_GEM_H
27
28 #define TYPE_CADENCE_GEM "cadence_gem"
29 #define CADENCE_GEM(obj) OBJECT_CHECK(CadenceGEMState, (obj), TYPE_CADENCE_GEM)
30
31 #include "net/net.h"
32 #include "hw/sysbus.h"
33
34 #define CADENCE_GEM_MAXREG (0x00000800 / 4) /* Last valid GEM address */
35
36 /* Max number of words in a DMA descriptor. */
37 #define DESC_MAX_NUM_WORDS 6
38
39 #define MAX_PRIORITY_QUEUES 8
40 #define MAX_TYPE1_SCREENERS 16
41 #define MAX_TYPE2_SCREENERS 16
42
43 #define MAX_JUMBO_FRAME_SIZE_MASK 0x3FFF
44 #define MAX_FRAME_SIZE MAX_JUMBO_FRAME_SIZE_MASK
45
46 typedef struct CadenceGEMState {
47 /*< private >*/
48 SysBusDevice parent_obj;
49
50 /*< public >*/
51 MemoryRegion iomem;
52 MemoryRegion *dma_mr;
53 AddressSpace dma_as;
54 NICState *nic;
55 NICConf conf;
56 qemu_irq irq[MAX_PRIORITY_QUEUES];
57
58 /* Static properties */
59 uint8_t num_priority_queues;
60 uint8_t num_type1_screeners;
61 uint8_t num_type2_screeners;
62 uint32_t revision;
63 uint16_t jumbo_max_len;
64
65 /* GEM registers backing store */
66 uint32_t regs[CADENCE_GEM_MAXREG];
67 /* Mask of register bits which are write only */
68 uint32_t regs_wo[CADENCE_GEM_MAXREG];
69 /* Mask of register bits which are read only */
70 uint32_t regs_ro[CADENCE_GEM_MAXREG];
71 /* Mask of register bits which are clear on read */
72 uint32_t regs_rtc[CADENCE_GEM_MAXREG];
73 /* Mask of register bits which are write 1 to clear */
74 uint32_t regs_w1c[CADENCE_GEM_MAXREG];
75
76 /* PHY registers backing store */
77 uint16_t phy_regs[32];
78
79 uint8_t phy_loop; /* Are we in phy loopback? */
80
81 /* The current DMA descriptor pointers */
82 uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
83 uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
84
85 uint8_t can_rx_state; /* Debug only */
86
87 uint8_t tx_packet[MAX_FRAME_SIZE];
88 uint8_t rx_packet[MAX_FRAME_SIZE];
89 uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
90
91 bool sar_active[4];
92 } CadenceGEMState;
93
94 #endif