Fix version for v6.2.0-rc2 release
[qemu.git] / include / hw / net / imx_fec.h
1 /*
2 * i.MX FEC/ENET Ethernet Controller emulation.
3 *
4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
5 *
6 * Based on Coldfire Fast Ethernet Controller emulation.
7 *
8 * Copyright (c) 2007 CodeSourcery.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #ifndef IMX_FEC_H
25 #define IMX_FEC_H
26 #include "qom/object.h"
27
28 #define TYPE_IMX_FEC "imx.fec"
29 OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
30
31 #define TYPE_IMX_ENET "imx.enet"
32
33 #include "hw/sysbus.h"
34 #include "net/net.h"
35
36 #define ENET_EIR 1
37 #define ENET_EIMR 2
38 #define ENET_RDAR 4
39 #define ENET_TDAR 5
40 #define ENET_ECR 9
41 #define ENET_MMFR 16
42 #define ENET_MSCR 17
43 #define ENET_MIBC 25
44 #define ENET_RCR 33
45 #define ENET_TCR 49
46 #define ENET_PALR 57
47 #define ENET_PAUR 58
48 #define ENET_OPD 59
49 #define ENET_IAUR 70
50 #define ENET_IALR 71
51 #define ENET_GAUR 72
52 #define ENET_GALR 73
53 #define ENET_TFWR 81
54 #define ENET_FRBR 83
55 #define ENET_FRSR 84
56 #define ENET_TDSR1 89
57 #define ENET_TDSR2 92
58 #define ENET_RDSR 96
59 #define ENET_TDSR 97
60 #define ENET_MRBR 98
61 #define ENET_RSFL 100
62 #define ENET_RSEM 101
63 #define ENET_RAEM 102
64 #define ENET_RAFL 103
65 #define ENET_TSEM 104
66 #define ENET_TAEM 105
67 #define ENET_TAFL 106
68 #define ENET_TIPG 107
69 #define ENET_FTRL 108
70 #define ENET_TACC 112
71 #define ENET_RACC 113
72 #define ENET_TDAR1 121
73 #define ENET_TDAR2 123
74 #define ENET_MIIGSK_CFGR 192
75 #define ENET_MIIGSK_ENR 194
76 #define ENET_ATCR 256
77 #define ENET_ATVR 257
78 #define ENET_ATOFF 258
79 #define ENET_ATPER 259
80 #define ENET_ATCOR 260
81 #define ENET_ATINC 261
82 #define ENET_ATSTMP 262
83 #define ENET_TGSR 385
84 #define ENET_TCSR0 386
85 #define ENET_TCCR0 387
86 #define ENET_TCSR1 388
87 #define ENET_TCCR1 389
88 #define ENET_TCSR2 390
89 #define ENET_TCCR2 391
90 #define ENET_TCSR3 392
91 #define ENET_TCCR3 393
92 #define ENET_MAX 400
93
94
95 /* EIR and EIMR */
96 #define ENET_INT_HB (1 << 31)
97 #define ENET_INT_BABR (1 << 30)
98 #define ENET_INT_BABT (1 << 29)
99 #define ENET_INT_GRA (1 << 28)
100 #define ENET_INT_TXF (1 << 27)
101 #define ENET_INT_TXB (1 << 26)
102 #define ENET_INT_RXF (1 << 25)
103 #define ENET_INT_RXB (1 << 24)
104 #define ENET_INT_MII (1 << 23)
105 #define ENET_INT_EBERR (1 << 22)
106 #define ENET_INT_LC (1 << 21)
107 #define ENET_INT_RL (1 << 20)
108 #define ENET_INT_UN (1 << 19)
109 #define ENET_INT_PLR (1 << 18)
110 #define ENET_INT_WAKEUP (1 << 17)
111 #define ENET_INT_TS_AVAIL (1 << 16)
112 #define ENET_INT_TS_TIMER (1 << 15)
113 #define ENET_INT_TXF2 (1 << 7)
114 #define ENET_INT_TXB2 (1 << 6)
115 #define ENET_INT_TXF1 (1 << 3)
116 #define ENET_INT_TXB1 (1 << 2)
117
118 #define ENET_INT_MAC (ENET_INT_HB | ENET_INT_BABR | ENET_INT_BABT | \
119 ENET_INT_GRA | ENET_INT_TXF | ENET_INT_TXB | \
120 ENET_INT_RXF | ENET_INT_RXB | ENET_INT_MII | \
121 ENET_INT_EBERR | ENET_INT_LC | ENET_INT_RL | \
122 ENET_INT_UN | ENET_INT_PLR | ENET_INT_WAKEUP | \
123 ENET_INT_TS_AVAIL | ENET_INT_TXF1 | \
124 ENET_INT_TXB1 | ENET_INT_TXF2 | ENET_INT_TXB2)
125
126 /* RDAR */
127 #define ENET_RDAR_RDAR (1 << 24)
128
129 /* TDAR */
130 #define ENET_TDAR_TDAR (1 << 24)
131
132 /* ECR */
133 #define ENET_ECR_RESET (1 << 0)
134 #define ENET_ECR_ETHEREN (1 << 1)
135 #define ENET_ECR_MAGICEN (1 << 2)
136 #define ENET_ECR_SLEEP (1 << 3)
137 #define ENET_ECR_EN1588 (1 << 4)
138 #define ENET_ECR_SPEED (1 << 5)
139 #define ENET_ECR_DBGEN (1 << 6)
140 #define ENET_ECR_STOPEN (1 << 7)
141 #define ENET_ECR_DSBWP (1 << 8)
142
143 /* MIBC */
144 #define ENET_MIBC_MIB_DIS (1 << 31)
145 #define ENET_MIBC_MIB_IDLE (1 << 30)
146 #define ENET_MIBC_MIB_CLEAR (1 << 29)
147
148 /* RCR */
149 #define ENET_RCR_LOOP (1 << 0)
150 #define ENET_RCR_DRT (1 << 1)
151 #define ENET_RCR_MII_MODE (1 << 2)
152 #define ENET_RCR_PROM (1 << 3)
153 #define ENET_RCR_BC_REJ (1 << 4)
154 #define ENET_RCR_FCE (1 << 5)
155 #define ENET_RCR_RGMII_EN (1 << 6)
156 #define ENET_RCR_RMII_MODE (1 << 8)
157 #define ENET_RCR_RMII_10T (1 << 9)
158 #define ENET_RCR_PADEN (1 << 12)
159 #define ENET_RCR_PAUFWD (1 << 13)
160 #define ENET_RCR_CRCFWD (1 << 14)
161 #define ENET_RCR_CFEN (1 << 15)
162 #define ENET_RCR_MAX_FL_SHIFT (16)
163 #define ENET_RCR_MAX_FL_LENGTH (14)
164 #define ENET_RCR_NLC (1 << 30)
165 #define ENET_RCR_GRS (1 << 31)
166
167 #define ENET_MAX_FRAME_SIZE (1 << ENET_RCR_MAX_FL_LENGTH)
168
169 /* TCR */
170 #define ENET_TCR_GTS (1 << 0)
171 #define ENET_TCR_FDEN (1 << 2)
172 #define ENET_TCR_TFC_PAUSE (1 << 3)
173 #define ENET_TCR_RFC_PAUSE (1 << 4)
174 #define ENET_TCR_ADDSEL_SHIFT (5)
175 #define ENET_TCR_ADDSEL_LENGTH (3)
176 #define ENET_TCR_CRCFWD (1 << 9)
177
178 /* RDSR */
179 #define ENET_TWFR_TFWR_SHIFT (0)
180 #define ENET_TWFR_TFWR_LENGTH (6)
181 #define ENET_TWFR_STRFWD (1 << 8)
182
183 #define ENET_RACC_SHIFT16 BIT(7)
184
185 /* Buffer Descriptor. */
186 typedef struct {
187 uint16_t length;
188 uint16_t flags;
189 uint32_t data;
190 } IMXFECBufDesc;
191
192 #define ENET_BD_R (1 << 15)
193 #define ENET_BD_E (1 << 15)
194 #define ENET_BD_O1 (1 << 14)
195 #define ENET_BD_W (1 << 13)
196 #define ENET_BD_O2 (1 << 12)
197 #define ENET_BD_L (1 << 11)
198 #define ENET_BD_TC (1 << 10)
199 #define ENET_BD_ABC (1 << 9)
200 #define ENET_BD_M (1 << 8)
201 #define ENET_BD_BC (1 << 7)
202 #define ENET_BD_MC (1 << 6)
203 #define ENET_BD_LG (1 << 5)
204 #define ENET_BD_NO (1 << 4)
205 #define ENET_BD_CR (1 << 2)
206 #define ENET_BD_OV (1 << 1)
207 #define ENET_BD_TR (1 << 0)
208
209 typedef struct {
210 uint16_t length;
211 uint16_t flags;
212 uint32_t data;
213 uint16_t status;
214 uint16_t option;
215 uint16_t checksum;
216 uint16_t head_proto;
217 uint32_t last_buffer;
218 uint32_t timestamp;
219 uint32_t reserved[2];
220 } IMXENETBufDesc;
221
222 #define ENET_BD_ME (1 << 15)
223 #define ENET_BD_TX_INT (1 << 14)
224 #define ENET_BD_TS (1 << 13)
225 #define ENET_BD_PINS (1 << 12)
226 #define ENET_BD_IINS (1 << 11)
227 #define ENET_BD_PE (1 << 10)
228 #define ENET_BD_CE (1 << 9)
229 #define ENET_BD_UC (1 << 8)
230 #define ENET_BD_RX_INT (1 << 7)
231
232 #define ENET_BD_TXE (1 << 15)
233 #define ENET_BD_UE (1 << 13)
234 #define ENET_BD_EE (1 << 12)
235 #define ENET_BD_FE (1 << 11)
236 #define ENET_BD_LCE (1 << 10)
237 #define ENET_BD_OE (1 << 9)
238 #define ENET_BD_TSE (1 << 8)
239 #define ENET_BD_ICE (1 << 5)
240 #define ENET_BD_PCR (1 << 4)
241 #define ENET_BD_VLAN (1 << 2)
242 #define ENET_BD_IPV6 (1 << 1)
243 #define ENET_BD_FRAG (1 << 0)
244
245 #define ENET_BD_BDU (1 << 31)
246
247 #define ENET_TX_RING_NUM 3
248
249 #define FSL_IMX25_FEC_SIZE 0x4000
250
251 struct IMXFECState {
252 /*< private >*/
253 SysBusDevice parent_obj;
254
255 /*< public >*/
256 NICState *nic;
257 NICConf conf;
258 qemu_irq irq[2];
259 MemoryRegion iomem;
260
261 uint32_t regs[ENET_MAX];
262 uint32_t rx_descriptor;
263
264 uint32_t tx_descriptor[ENET_TX_RING_NUM];
265 uint32_t tx_ring_num;
266
267 uint32_t phy_status;
268 uint32_t phy_control;
269 uint32_t phy_advertise;
270 uint32_t phy_int;
271 uint32_t phy_int_mask;
272 uint32_t phy_num;
273
274 bool is_fec;
275
276 /* Buffer used to assemble a Tx frame */
277 uint8_t frame[ENET_MAX_FRAME_SIZE];
278 };
279
280 #endif