Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging
[qemu.git] / include / hw / net / npcm7xx_emc.h
1 /*
2 * Nuvoton NPCM7xx EMC Module
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #ifndef NPCM7XX_EMC_H
18 #define NPCM7XX_EMC_H
19
20 #include "hw/irq.h"
21 #include "hw/sysbus.h"
22 #include "net/net.h"
23
24 /* 32-bit register indices. */
25 enum NPCM7xxPWMRegister {
26 /* Control registers. */
27 REG_CAMCMR,
28 REG_CAMEN,
29
30 /* There are 16 CAMn[ML] registers. */
31 REG_CAMM_BASE,
32 REG_CAML_BASE,
33 REG_CAMML_LAST = 0x21,
34
35 REG_TXDLSA = 0x22,
36 REG_RXDLSA,
37 REG_MCMDR,
38 REG_MIID,
39 REG_MIIDA,
40 REG_FFTCR,
41 REG_TSDR,
42 REG_RSDR,
43 REG_DMARFC,
44 REG_MIEN,
45
46 /* Status registers. */
47 REG_MISTA,
48 REG_MGSTA,
49 REG_MPCNT,
50 REG_MRPC,
51 REG_MRPCC,
52 REG_MREPC,
53 REG_DMARFS,
54 REG_CTXDSA,
55 REG_CTXBSA,
56 REG_CRXDSA,
57 REG_CRXBSA,
58
59 NPCM7XX_NUM_EMC_REGS,
60 };
61
62 /* REG_CAMCMR fields */
63 /* Enable CAM Compare */
64 #define REG_CAMCMR_ECMP (1 << 4)
65 /* Complement CAM Compare */
66 #define REG_CAMCMR_CCAM (1 << 3)
67 /* Accept Broadcast Packet */
68 #define REG_CAMCMR_ABP (1 << 2)
69 /* Accept Multicast Packet */
70 #define REG_CAMCMR_AMP (1 << 1)
71 /* Accept Unicast Packet */
72 #define REG_CAMCMR_AUP (1 << 0)
73
74 /* REG_MCMDR fields */
75 /* Software Reset */
76 #define REG_MCMDR_SWR (1 << 24)
77 /* Internal Loopback Select */
78 #define REG_MCMDR_LBK (1 << 21)
79 /* Operation Mode Select */
80 #define REG_MCMDR_OPMOD (1 << 20)
81 /* Enable MDC Clock Generation */
82 #define REG_MCMDR_ENMDC (1 << 19)
83 /* Full-Duplex Mode Select */
84 #define REG_MCMDR_FDUP (1 << 18)
85 /* Enable SQE Checking */
86 #define REG_MCMDR_ENSEQ (1 << 17)
87 /* Send PAUSE Frame */
88 #define REG_MCMDR_SDPZ (1 << 16)
89 /* No Defer */
90 #define REG_MCMDR_NDEF (1 << 9)
91 /* Frame Transmission On */
92 #define REG_MCMDR_TXON (1 << 8)
93 /* Strip CRC Checksum */
94 #define REG_MCMDR_SPCRC (1 << 5)
95 /* Accept CRC Error Packet */
96 #define REG_MCMDR_AEP (1 << 4)
97 /* Accept Control Packet */
98 #define REG_MCMDR_ACP (1 << 3)
99 /* Accept Runt Packet */
100 #define REG_MCMDR_ARP (1 << 2)
101 /* Accept Long Packet */
102 #define REG_MCMDR_ALP (1 << 1)
103 /* Frame Reception On */
104 #define REG_MCMDR_RXON (1 << 0)
105
106 /* REG_MIEN fields */
107 /* Enable Transmit Descriptor Unavailable Interrupt */
108 #define REG_MIEN_ENTDU (1 << 23)
109 /* Enable Transmit Completion Interrupt */
110 #define REG_MIEN_ENTXCP (1 << 18)
111 /* Enable Transmit Interrupt */
112 #define REG_MIEN_ENTXINTR (1 << 16)
113 /* Enable Receive Descriptor Unavailable Interrupt */
114 #define REG_MIEN_ENRDU (1 << 10)
115 /* Enable Receive Good Interrupt */
116 #define REG_MIEN_ENRXGD (1 << 4)
117 /* Enable Receive Interrupt */
118 #define REG_MIEN_ENRXINTR (1 << 0)
119
120 /* REG_MISTA fields */
121 /* TODO: Add error fields and support simulated errors? */
122 /* Transmit Bus Error Interrupt */
123 #define REG_MISTA_TXBERR (1 << 24)
124 /* Transmit Descriptor Unavailable Interrupt */
125 #define REG_MISTA_TDU (1 << 23)
126 /* Transmit Completion Interrupt */
127 #define REG_MISTA_TXCP (1 << 18)
128 /* Transmit Interrupt */
129 #define REG_MISTA_TXINTR (1 << 16)
130 /* Receive Bus Error Interrupt */
131 #define REG_MISTA_RXBERR (1 << 11)
132 /* Receive Descriptor Unavailable Interrupt */
133 #define REG_MISTA_RDU (1 << 10)
134 /* DMA Early Notification Interrupt */
135 #define REG_MISTA_DENI (1 << 9)
136 /* Maximum Frame Length Interrupt */
137 #define REG_MISTA_DFOI (1 << 8)
138 /* Receive Good Interrupt */
139 #define REG_MISTA_RXGD (1 << 4)
140 /* Packet Too Long Interrupt */
141 #define REG_MISTA_PTLE (1 << 3)
142 /* Receive Interrupt */
143 #define REG_MISTA_RXINTR (1 << 0)
144
145 /* REG_MGSTA fields */
146 /* Transmission Halted */
147 #define REG_MGSTA_TXHA (1 << 11)
148 /* Receive Halted */
149 #define REG_MGSTA_RXHA (1 << 11)
150
151 /* REG_DMARFC fields */
152 /* Maximum Receive Frame Length */
153 #define REG_DMARFC_RXMS(word) extract32((word), 0, 16)
154
155 /* REG MIIDA fields */
156 /* Busy Bit */
157 #define REG_MIIDA_BUSY (1 << 17)
158
159 /* Transmit and receive descriptors */
160 typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc;
161 typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc;
162
163 struct NPCM7xxEMCTxDesc {
164 uint32_t flags;
165 uint32_t txbsa;
166 uint32_t status_and_length;
167 uint32_t ntxdsa;
168 };
169
170 struct NPCM7xxEMCRxDesc {
171 uint32_t status_and_length;
172 uint32_t rxbsa;
173 uint32_t reserved;
174 uint32_t nrxdsa;
175 };
176
177 /* NPCM7xxEMCTxDesc.flags values */
178 /* Owner: 0 = cpu, 1 = emc */
179 #define TX_DESC_FLAG_OWNER_MASK (1 << 31)
180 /* Transmit interrupt enable */
181 #define TX_DESC_FLAG_INTEN (1 << 2)
182 /* CRC append */
183 #define TX_DESC_FLAG_CRCAPP (1 << 1)
184 /* Padding enable */
185 #define TX_DESC_FLAG_PADEN (1 << 0)
186
187 /* NPCM7xxEMCTxDesc.status_and_length values */
188 /* Collision count */
189 #define TX_DESC_STATUS_CCNT_SHIFT 28
190 #define TX_DESC_STATUS_CCNT_BITSIZE 4
191 /* SQE error */
192 #define TX_DESC_STATUS_SQE (1 << 26)
193 /* Transmission paused */
194 #define TX_DESC_STATUS_PAU (1 << 25)
195 /* P transmission halted */
196 #define TX_DESC_STATUS_TXHA (1 << 24)
197 /* Late collision */
198 #define TX_DESC_STATUS_LC (1 << 23)
199 /* Transmission abort */
200 #define TX_DESC_STATUS_TXABT (1 << 22)
201 /* No carrier sense */
202 #define TX_DESC_STATUS_NCS (1 << 21)
203 /* Defer exceed */
204 #define TX_DESC_STATUS_EXDEF (1 << 20)
205 /* Transmission complete */
206 #define TX_DESC_STATUS_TXCP (1 << 19)
207 /* Transmission deferred */
208 #define TX_DESC_STATUS_DEF (1 << 17)
209 /* Transmit interrupt */
210 #define TX_DESC_STATUS_TXINTR (1 << 16)
211
212 #define TX_DESC_PKT_LEN(word) extract32((word), 0, 16)
213
214 /* Transmit buffer start address */
215 #define TX_DESC_TXBSA(word) ((uint32_t) (word) & ~3u)
216
217 /* Next transmit descriptor start address */
218 #define TX_DESC_NTXDSA(word) ((uint32_t) (word) & ~3u)
219
220 /* NPCM7xxEMCRxDesc.status_and_length values */
221 /* Owner: 0b00 = cpu, 0b01 = undefined, 0b10 = emc, 0b11 = undefined */
222 #define RX_DESC_STATUS_OWNER_SHIFT 30
223 #define RX_DESC_STATUS_OWNER_BITSIZE 2
224 #define RX_DESC_STATUS_OWNER_MASK (3 << RX_DESC_STATUS_OWNER_SHIFT)
225 /* Runt packet */
226 #define RX_DESC_STATUS_RP (1 << 22)
227 /* Alignment error */
228 #define RX_DESC_STATUS_ALIE (1 << 21)
229 /* Frame reception complete */
230 #define RX_DESC_STATUS_RXGD (1 << 20)
231 /* Packet too long */
232 #define RX_DESC_STATUS_PTLE (1 << 19)
233 /* CRC error */
234 #define RX_DESC_STATUS_CRCE (1 << 17)
235 /* Receive interrupt */
236 #define RX_DESC_STATUS_RXINTR (1 << 16)
237
238 #define RX_DESC_PKT_LEN(word) extract32((word), 0, 16)
239
240 /* Receive buffer start address */
241 #define RX_DESC_RXBSA(word) ((uint32_t) (word) & ~3u)
242
243 /* Next receive descriptor start address */
244 #define RX_DESC_NRXDSA(word) ((uint32_t) (word) & ~3u)
245
246 /* Minimum packet length, when TX_DESC_FLAG_PADEN is set. */
247 #define MIN_PACKET_LENGTH 64
248
249 struct NPCM7xxEMCState {
250 /*< private >*/
251 SysBusDevice parent;
252 /*< public >*/
253
254 MemoryRegion iomem;
255
256 qemu_irq tx_irq;
257 qemu_irq rx_irq;
258
259 NICState *nic;
260 NICConf conf;
261
262 /* 0 or 1, for log messages */
263 uint8_t emc_num;
264
265 uint32_t regs[NPCM7XX_NUM_EMC_REGS];
266
267 /*
268 * tx is active. Set to true by TSDR and then switches off when out of
269 * descriptors. If the TXON bit in REG_MCMDR is off then this is off.
270 */
271 bool tx_active;
272
273 /*
274 * rx is active. Set to true by RSDR and then switches off when out of
275 * descriptors. If the RXON bit in REG_MCMDR is off then this is off.
276 */
277 bool rx_active;
278 };
279
280 typedef struct NPCM7xxEMCState NPCM7xxEMCState;
281
282 #define TYPE_NPCM7XX_EMC "npcm7xx-emc"
283 #define NPCM7XX_EMC(obj) \
284 OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
285
286 #endif /* NPCM7XX_EMC_H */