ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / pci-host / pnv_phb3.h
1 /*
2 * QEMU PowerPC PowerNV (POWER8) PHB3 model
3 *
4 * Copyright (c) 2014-2020, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #ifndef PCI_HOST_PNV_PHB3_H
11 #define PCI_HOST_PNV_PHB3_H
12
13 #include "hw/pci/pcie_host.h"
14 #include "hw/pci/pcie_port.h"
15 #include "hw/ppc/xics.h"
16
17 typedef struct PnvPHB3 PnvPHB3;
18
19 /*
20 * PHB3 XICS Source for MSIs
21 */
22 #define TYPE_PHB3_MSI "phb3-msi"
23 #define PHB3_MSI(obj) OBJECT_CHECK(Phb3MsiState, (obj), TYPE_PHB3_MSI)
24
25 #define PHB3_MAX_MSI 2048
26
27 typedef struct Phb3MsiState {
28 ICSState ics;
29 qemu_irq *qirqs;
30
31 PnvPHB3 *phb;
32 uint64_t rba[PHB3_MAX_MSI / 64];
33 uint32_t rba_sum;
34 } Phb3MsiState;
35
36 void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
37 uint32_t count);
38 void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
39 int32_t dev_pe);
40 void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
41 void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon);
42
43
44 /*
45 * We have one such address space wrapper per possible device under
46 * the PHB since they need to be assigned statically at qemu device
47 * creation time. The relationship to a PE is done later dynamically.
48 * This means we can potentially create a lot of these guys. Q35
49 * stores them as some kind of radix tree but we never really need to
50 * do fast lookups so instead we simply keep a QLIST of them for now,
51 * we can add the radix if needed later on.
52 *
53 * We do cache the PE number to speed things up a bit though.
54 */
55 typedef struct PnvPhb3DMASpace {
56 PCIBus *bus;
57 uint8_t devfn;
58 int pe_num; /* Cached PE number */
59 #define PHB_INVALID_PE (-1)
60 PnvPHB3 *phb;
61 AddressSpace dma_as;
62 IOMMUMemoryRegion dma_mr;
63 MemoryRegion msi32_mr;
64 MemoryRegion msi64_mr;
65 QLIST_ENTRY(PnvPhb3DMASpace) list;
66 } PnvPhb3DMASpace;
67
68 /*
69 * PHB3 Power Bus Common Queue
70 */
71 #define TYPE_PNV_PBCQ "pnv-pbcq"
72 #define PNV_PBCQ(obj) OBJECT_CHECK(PnvPBCQState, (obj), TYPE_PNV_PBCQ)
73
74 typedef struct PnvPBCQState {
75 DeviceState parent;
76
77 uint32_t nest_xbase;
78 uint32_t spci_xbase;
79 uint32_t pci_xbase;
80 #define PBCQ_NEST_REGS_COUNT 0x46
81 #define PBCQ_PCI_REGS_COUNT 0x15
82 #define PBCQ_SPCI_REGS_COUNT 0x5
83
84 uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
85 uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
86 uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
87 MemoryRegion mmbar0;
88 MemoryRegion mmbar1;
89 MemoryRegion phbbar;
90 uint64_t mmio0_base;
91 uint64_t mmio0_size;
92 uint64_t mmio1_base;
93 uint64_t mmio1_size;
94 PnvPHB3 *phb;
95
96 MemoryRegion xscom_nest_regs;
97 MemoryRegion xscom_pci_regs;
98 MemoryRegion xscom_spci_regs;
99 } PnvPBCQState;
100
101 /*
102 * PHB3 PCIe Root port
103 */
104 #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root-bus"
105
106 #define TYPE_PNV_PHB3_ROOT_PORT "pnv-phb3-root-port"
107
108 typedef struct PnvPHB3RootPort {
109 PCIESlot parent_obj;
110 } PnvPHB3RootPort;
111
112 /*
113 * PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
114 */
115 #define TYPE_PNV_PHB3 "pnv-phb3"
116 #define PNV_PHB3(obj) OBJECT_CHECK(PnvPHB3, (obj), TYPE_PNV_PHB3)
117
118 #define PNV_PHB3_NUM_M64 16
119 #define PNV_PHB3_NUM_REGS (0x1000 >> 3)
120 #define PNV_PHB3_NUM_LSI 8
121 #define PNV_PHB3_NUM_PE 256
122
123 #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60)
124
125 struct PnvPHB3 {
126 PCIExpressHost parent_obj;
127
128 uint32_t chip_id;
129 uint32_t phb_id;
130 char bus_path[8];
131
132 uint64_t regs[PNV_PHB3_NUM_REGS];
133 MemoryRegion mr_regs;
134
135 MemoryRegion mr_m32;
136 MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
137 MemoryRegion pci_mmio;
138 MemoryRegion pci_io;
139
140 uint64_t ioda_LIST[8];
141 uint64_t ioda_LXIVT[8];
142 uint64_t ioda_TVT[512];
143 uint64_t ioda_M64BT[16];
144 uint64_t ioda_MDT[256];
145 uint64_t ioda_PEEV[4];
146
147 uint32_t total_irq;
148 ICSState lsis;
149 qemu_irq *qirqs;
150 Phb3MsiState msis;
151
152 PnvPBCQState pbcq;
153
154 PnvPHB3RootPort root;
155
156 QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
157 };
158
159 uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
160 void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
161 void pnv_phb3_update_regions(PnvPHB3 *phb);
162 void pnv_phb3_remap_irqs(PnvPHB3 *phb);
163
164 #endif /* PCI_HOST_PNV_PHB3_H */