ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / pci-host / q35.h
1 /*
2 * q35.h
3 *
4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see <http://www.gnu.org/licenses/>
20 */
21
22 #ifndef HW_Q35_H
23 #define HW_Q35_H
24
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pcie_host.h"
27 #include "hw/pci-host/pam.h"
28 #include "qemu/units.h"
29 #include "qemu/range.h"
30
31 #define TYPE_Q35_HOST_DEVICE "q35-pcihost"
32 #define Q35_HOST_DEVICE(obj) \
33 OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE)
34
35 #define TYPE_MCH_PCI_DEVICE "mch"
36 #define MCH_PCI_DEVICE(obj) \
37 OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
38
39 typedef struct MCHPCIState {
40 /*< private >*/
41 PCIDevice parent_obj;
42 /*< public >*/
43
44 MemoryRegion *ram_memory;
45 MemoryRegion *pci_address_space;
46 MemoryRegion *system_memory;
47 MemoryRegion *address_space_io;
48 PAMMemoryRegion pam_regions[13];
49 MemoryRegion smram_region, open_high_smram;
50 MemoryRegion smram, low_smram, high_smram;
51 MemoryRegion tseg_blackhole, tseg_window;
52 MemoryRegion smbase_blackhole, smbase_window;
53 bool has_smram_at_smbase;
54 Range pci_hole;
55 uint64_t below_4g_mem_size;
56 uint64_t above_4g_mem_size;
57 uint64_t pci_hole64_size;
58 uint32_t short_root_bus;
59 uint16_t ext_tseg_mbytes;
60 } MCHPCIState;
61
62 typedef struct Q35PCIHost {
63 /*< private >*/
64 PCIExpressHost parent_obj;
65 /*< public >*/
66
67 bool pci_hole64_fix;
68 MCHPCIState mch;
69 } Q35PCIHost;
70
71 #define Q35_MASK(bit, ms_bit, ls_bit) \
72 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
73
74 /*
75 * gmch part
76 */
77
78 #define MCH_HOST_PROP_RAM_MEM "ram-mem"
79 #define MCH_HOST_PROP_PCI_MEM "pci-mem"
80 #define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
81 #define MCH_HOST_PROP_IO_MEM "io-mem"
82
83 /* PCI configuration */
84 #define MCH_HOST_BRIDGE "MCH"
85
86 #define MCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
87 #define MCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
88
89 /* D0:F0 configuration space */
90 #define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
91
92 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES 0x50
93 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE 2
94 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY 0xffff
95 #define MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX 0xfff
96
97 #define MCH_HOST_BRIDGE_SMBASE_SIZE (128 * KiB)
98 #define MCH_HOST_BRIDGE_SMBASE_ADDR 0x30000
99 #define MCH_HOST_BRIDGE_F_SMBASE 0x9c
100 #define MCH_HOST_BRIDGE_F_SMBASE_QUERY 0xff
101 #define MCH_HOST_BRIDGE_F_SMBASE_IN_RAM 0x01
102 #define MCH_HOST_BRIDGE_F_SMBASE_LCK 0x02
103
104 #define MCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
105 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
106 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000
107 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */
108 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28)
109 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
110 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
111 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
112 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
113 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
114 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
115 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
116 #define MCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
117
118 #define MCH_HOST_BRIDGE_PAM_NB 7
119 #define MCH_HOST_BRIDGE_PAM_SIZE 7
120 #define MCH_HOST_BRIDGE_PAM0 0x90
121 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
122 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
123 #define MCH_HOST_BRIDGE_PAM1 0x91
124 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
125 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
126 #define MCH_HOST_BRIDGE_PAM2 0x92
127 #define MCH_HOST_BRIDGE_PAM3 0x93
128 #define MCH_HOST_BRIDGE_PAM4 0x94
129 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
130 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
131 #define MCH_HOST_BRIDGE_PAM5 0x95
132 #define MCH_HOST_BRIDGE_PAM6 0x96
133 #define MCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
134 #define MCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
135 #define MCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
136 #define MCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
137 #define MCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
138 #define MCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
139 #define MCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
140 #define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
141 #define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
142
143 #define MCH_HOST_BRIDGE_SMRAM 0x9d
144 #define MCH_HOST_BRIDGE_SMRAM_SIZE 2
145 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
146 #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
147 #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
148 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
149 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
150 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
151 #define MCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
152 #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
153 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
154 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
155 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \
156 MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG
157 #define MCH_HOST_BRIDGE_SMRAM_WMASK \
158 (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \
159 MCH_HOST_BRIDGE_SMRAM_D_CLS | \
160 MCH_HOST_BRIDGE_SMRAM_D_LCK | \
161 MCH_HOST_BRIDGE_SMRAM_G_SMRAME)
162 #define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \
163 MCH_HOST_BRIDGE_SMRAM_D_CLS
164
165 #define MCH_HOST_BRIDGE_ESMRAMC 0x9e
166 #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7))
167 #define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 6))
168 #define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 5))
169 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 4))
170 #define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 3))
171 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
172 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
173 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
174 #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
175 #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
176 #define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \
177 (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \
178 MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \
179 MCH_HOST_BRIDGE_ESMRAMC_SM_L2)
180 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK \
181 (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \
182 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \
183 MCH_HOST_BRIDGE_ESMRAMC_T_EN)
184 #define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0
185
186 /* D1:F0 PCIE* port*/
187 #define MCH_PCIE_DEV 1
188 #define MCH_PCIE_FUNC 0
189
190 uint64_t mch_mcfg_base(void);
191
192 /*
193 * Arbitrary but unique BNF number for IOAPIC device.
194 *
195 * TODO: make sure there would have no conflict with real PCI bus
196 */
197 #define Q35_PSEUDO_BUS_PLATFORM (0xff)
198 #define Q35_PSEUDO_DEVFN_IOAPIC (0x00)
199
200 #endif /* HW_Q35_H */