ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / pci-host / sabre.h
1 #ifndef HW_PCI_HOST_SABRE_H
2 #define HW_PCI_HOST_SABRE_H
3
4 #include "hw/pci/pci.h"
5 #include "hw/pci/pci_host.h"
6 #include "hw/sparc/sun4u_iommu.h"
7
8 #define MAX_IVEC 0x40
9
10 /* OBIO IVEC IRQs */
11 #define OBIO_HDD_IRQ 0x20
12 #define OBIO_NIC_IRQ 0x21
13 #define OBIO_LPT_IRQ 0x22
14 #define OBIO_FDD_IRQ 0x27
15 #define OBIO_KBD_IRQ 0x29
16 #define OBIO_MSE_IRQ 0x2a
17 #define OBIO_SER_IRQ 0x2b
18
19 typedef struct SabrePCIState {
20 PCIDevice parent_obj;
21 } SabrePCIState;
22
23 #define TYPE_SABRE_PCI_DEVICE "sabre-pci"
24 #define SABRE_PCI_DEVICE(obj) \
25 OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE)
26
27 typedef struct SabreState {
28 PCIHostState parent_obj;
29
30 hwaddr special_base;
31 hwaddr mem_base;
32 MemoryRegion sabre_config;
33 MemoryRegion pci_config;
34 MemoryRegion pci_mmio;
35 MemoryRegion pci_ioport;
36 uint64_t pci_irq_in;
37 IOMMUState *iommu;
38 PCIBridge *bridgeA;
39 PCIBridge *bridgeB;
40 uint32_t pci_control[16];
41 uint32_t pci_irq_map[8];
42 uint32_t pci_err_irq_map[4];
43 uint32_t obio_irq_map[32];
44 qemu_irq ivec_irqs[MAX_IVEC];
45 unsigned int irq_request;
46 uint32_t reset_control;
47 unsigned int nr_resets;
48 } SabreState;
49
50 #define TYPE_SABRE "sabre"
51 #define SABRE_DEVICE(obj) \
52 OBJECT_CHECK(SabreState, (obj), TYPE_SABRE)
53
54 #endif