block/export: Add query-block-exports
[qemu.git] / include / hw / pci / pci.h
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "exec/memory.h"
5 #include "sysemu/dma.h"
6
7 /* PCI includes legacy ISA access. */
8 #include "hw/isa/isa.h"
9
10 #include "hw/pci/pcie.h"
11 #include "qom/object.h"
12
13 extern bool pci_available;
14
15 /* PCI bus */
16
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
20 #define PCI_FUNC(devfn) ((devfn) & 0x07)
21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
22 #define PCI_BUS_MAX 256
23 #define PCI_DEVFN_MAX 256
24 #define PCI_SLOT_MAX 32
25 #define PCI_FUNC_MAX 8
26
27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
28 #include "hw/pci/pci_ids.h"
29
30 /* QEMU-specific Vendor and Device ID definitions */
31
32 /* IBM (0x1014) */
33 #define PCI_DEVICE_ID_IBM_440GX 0x027f
34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
35
36 /* Hitachi (0x1054) */
37 #define PCI_VENDOR_ID_HITACHI 0x1054
38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
39
40 /* Apple (0x106b) */
41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
46
47 /* Realtek (0x10ec) */
48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
49
50 /* Xilinx (0x10ee) */
51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
52
53 /* Marvell (0x11ab) */
54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
55
56 /* QEMU/Bochs VGA (0x1234) */
57 #define PCI_VENDOR_ID_QEMU 0x1234
58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
59 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112
60
61 /* VMWare (0x15ad) */
62 #define PCI_VENDOR_ID_VMWARE 0x15ad
63 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
64 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
65 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
66 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
67 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
68 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
69 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
70
71 /* Intel (0x8086) */
72 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
73 #define PCI_DEVICE_ID_INTEL_82557 0x1229
74 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
75
76 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
77 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
78 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
79 #define PCI_SUBDEVICE_ID_QEMU 0x1100
80
81 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
82 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
83 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
85 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
86 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
87 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
88 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
89 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
90 #define PCI_DEVICE_ID_VIRTIO_IOMMU 0x1014
91 #define PCI_DEVICE_ID_VIRTIO_MEM 0x1015
92
93 #define PCI_VENDOR_ID_REDHAT 0x1b36
94 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
95 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
96 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
97 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
98 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
99 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
100 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
101 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
102 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
103 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
104 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
105 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
106 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
107 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
108 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
109 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
110
111 #define FMT_PCIBUS PRIx64
112
113 typedef uint64_t pcibus_t;
114
115 struct PCIHostDeviceAddress {
116 unsigned int domain;
117 unsigned int bus;
118 unsigned int slot;
119 unsigned int function;
120 };
121
122 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
123 uint32_t address, uint32_t data, int len);
124 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
125 uint32_t address, int len);
126 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
127 pcibus_t addr, pcibus_t size, int type);
128 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
129
130 typedef struct PCIIORegion {
131 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
132 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
133 pcibus_t size;
134 uint8_t type;
135 MemoryRegion *memory;
136 MemoryRegion *address_space;
137 } PCIIORegion;
138
139 #define PCI_ROM_SLOT 6
140 #define PCI_NUM_REGIONS 7
141
142 enum {
143 QEMU_PCI_VGA_MEM,
144 QEMU_PCI_VGA_IO_LO,
145 QEMU_PCI_VGA_IO_HI,
146 QEMU_PCI_VGA_NUM_REGIONS,
147 };
148
149 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
150 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
151 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
152 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
153 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
154 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
155
156 #include "hw/pci/pci_regs.h"
157
158 /* PCI HEADER_TYPE */
159 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
160
161 /* Size of the standard PCI config header */
162 #define PCI_CONFIG_HEADER_SIZE 0x40
163 /* Size of the standard PCI config space */
164 #define PCI_CONFIG_SPACE_SIZE 0x100
165 /* Size of the standard PCIe config space: 4KB */
166 #define PCIE_CONFIG_SPACE_SIZE 0x1000
167
168 #define PCI_NUM_PINS 4 /* A-D */
169
170 /* Bits in cap_present field. */
171 enum {
172 QEMU_PCI_CAP_MSI = 0x1,
173 QEMU_PCI_CAP_MSIX = 0x2,
174 QEMU_PCI_CAP_EXPRESS = 0x4,
175
176 /* multifunction capable device */
177 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
178 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
179
180 /* command register SERR bit enabled - unused since QEMU v5.0 */
181 #define QEMU_PCI_CAP_SERR_BITNR 4
182 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
183 /* Standard hot plug controller. */
184 #define QEMU_PCI_SHPC_BITNR 5
185 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
186 #define QEMU_PCI_SLOTID_BITNR 6
187 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
188 /* PCI Express capability - Power Controller Present */
189 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
190 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
191 /* Link active status in endpoint capability is always set */
192 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
193 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
194 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
195 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
196 };
197
198 #define TYPE_PCI_DEVICE "pci-device"
199 typedef struct PCIDeviceClass PCIDeviceClass;
200 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
201 PCI_DEVICE, TYPE_PCI_DEVICE)
202
203 /* Implemented by devices that can be plugged on PCI Express buses */
204 #define INTERFACE_PCIE_DEVICE "pci-express-device"
205
206 /* Implemented by devices that can be plugged on Conventional PCI buses */
207 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
208
209 typedef struct PCIINTxRoute {
210 enum {
211 PCI_INTX_ENABLED,
212 PCI_INTX_INVERTED,
213 PCI_INTX_DISABLED,
214 } mode;
215 int irq;
216 } PCIINTxRoute;
217
218 struct PCIDeviceClass {
219 DeviceClass parent_class;
220
221 void (*realize)(PCIDevice *dev, Error **errp);
222 PCIUnregisterFunc *exit;
223 PCIConfigReadFunc *config_read;
224 PCIConfigWriteFunc *config_write;
225
226 uint16_t vendor_id;
227 uint16_t device_id;
228 uint8_t revision;
229 uint16_t class_id;
230 uint16_t subsystem_vendor_id; /* only for header type = 0 */
231 uint16_t subsystem_id; /* only for header type = 0 */
232
233 /*
234 * pci-to-pci bridge or normal device.
235 * This doesn't mean pci host switch.
236 * When card bus bridge is supported, this would be enhanced.
237 */
238 bool is_bridge;
239
240 /* rom bar */
241 const char *romfile;
242 };
243
244 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
245 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
246 MSIMessage msg);
247 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
248 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
249 unsigned int vector_start,
250 unsigned int vector_end);
251
252 enum PCIReqIDType {
253 PCI_REQ_ID_INVALID = 0,
254 PCI_REQ_ID_BDF,
255 PCI_REQ_ID_SECONDARY_BUS,
256 PCI_REQ_ID_MAX,
257 };
258 typedef enum PCIReqIDType PCIReqIDType;
259
260 struct PCIReqIDCache {
261 PCIDevice *dev;
262 PCIReqIDType type;
263 };
264 typedef struct PCIReqIDCache PCIReqIDCache;
265
266 struct PCIDevice {
267 DeviceState qdev;
268 bool partially_hotplugged;
269
270 /* PCI config space */
271 uint8_t *config;
272
273 /* Used to enable config checks on load. Note that writable bits are
274 * never checked even if set in cmask. */
275 uint8_t *cmask;
276
277 /* Used to implement R/W bytes */
278 uint8_t *wmask;
279
280 /* Used to implement RW1C(Write 1 to Clear) bytes */
281 uint8_t *w1cmask;
282
283 /* Used to allocate config space for capabilities. */
284 uint8_t *used;
285
286 /* the following fields are read only */
287 int32_t devfn;
288 /* Cached device to fetch requester ID from, to avoid the PCI
289 * tree walking every time we invoke PCI request (e.g.,
290 * MSI). For conventional PCI root complex, this field is
291 * meaningless. */
292 PCIReqIDCache requester_id_cache;
293 char name[64];
294 PCIIORegion io_regions[PCI_NUM_REGIONS];
295 AddressSpace bus_master_as;
296 MemoryRegion bus_master_container_region;
297 MemoryRegion bus_master_enable_region;
298
299 /* do not access the following fields */
300 PCIConfigReadFunc *config_read;
301 PCIConfigWriteFunc *config_write;
302
303 /* Legacy PCI VGA regions */
304 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
305 bool has_vga;
306
307 /* Current IRQ levels. Used internally by the generic PCI code. */
308 uint8_t irq_state;
309
310 /* Capability bits */
311 uint32_t cap_present;
312
313 /* Offset of MSI-X capability in config space */
314 uint8_t msix_cap;
315
316 /* MSI-X entries */
317 int msix_entries_nr;
318
319 /* Space to store MSIX table & pending bit array */
320 uint8_t *msix_table;
321 uint8_t *msix_pba;
322 /* MemoryRegion container for msix exclusive BAR setup */
323 MemoryRegion msix_exclusive_bar;
324 /* Memory Regions for MSIX table and pending bit entries. */
325 MemoryRegion msix_table_mmio;
326 MemoryRegion msix_pba_mmio;
327 /* Reference-count for entries actually in use by driver. */
328 unsigned *msix_entry_used;
329 /* MSIX function mask set or MSIX disabled */
330 bool msix_function_masked;
331 /* Version id needed for VMState */
332 int32_t version_id;
333
334 /* Offset of MSI capability in config space */
335 uint8_t msi_cap;
336
337 /* PCI Express */
338 PCIExpressDevice exp;
339
340 /* SHPC */
341 SHPCDevice *shpc;
342
343 /* Location of option rom */
344 char *romfile;
345 bool has_rom;
346 MemoryRegion rom;
347 uint32_t rom_bar;
348
349 /* INTx routing notifier */
350 PCIINTxRoutingNotifier intx_routing_notifier;
351
352 /* MSI-X notifiers */
353 MSIVectorUseNotifier msix_vector_use_notifier;
354 MSIVectorReleaseNotifier msix_vector_release_notifier;
355 MSIVectorPollNotifier msix_vector_poll_notifier;
356
357 /* ID of standby device in net_failover pair */
358 char *failover_pair_id;
359 };
360
361 void pci_register_bar(PCIDevice *pci_dev, int region_num,
362 uint8_t attr, MemoryRegion *memory);
363 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
364 MemoryRegion *io_lo, MemoryRegion *io_hi);
365 void pci_unregister_vga(PCIDevice *pci_dev);
366 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
367
368 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
369 uint8_t offset, uint8_t size,
370 Error **errp);
371
372 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
373
374 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
375
376
377 uint32_t pci_default_read_config(PCIDevice *d,
378 uint32_t address, int len);
379 void pci_default_write_config(PCIDevice *d,
380 uint32_t address, uint32_t val, int len);
381 void pci_device_save(PCIDevice *s, QEMUFile *f);
382 int pci_device_load(PCIDevice *s, QEMUFile *f);
383 MemoryRegion *pci_address_space(PCIDevice *dev);
384 MemoryRegion *pci_address_space_io(PCIDevice *dev);
385
386 /*
387 * Should not normally be used by devices. For use by sPAPR target
388 * where QEMU emulates firmware.
389 */
390 int pci_bar(PCIDevice *d, int reg);
391
392 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
393 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
394 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
395
396 #define TYPE_PCI_BUS "PCI"
397 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
398 #define TYPE_PCIE_BUS "PCIE"
399
400 bool pci_bus_is_express(PCIBus *bus);
401
402 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
403 const char *name,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min, const char *typename);
407 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
408 MemoryRegion *address_space_mem,
409 MemoryRegion *address_space_io,
410 uint8_t devfn_min, const char *typename);
411 void pci_root_bus_cleanup(PCIBus *bus);
412 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
413 void *irq_opaque, int nirq);
414 void pci_bus_irqs_cleanup(PCIBus *bus);
415 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
416 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
417 static inline int pci_swizzle(int slot, int pin)
418 {
419 return (slot + pin) % PCI_NUM_PINS;
420 }
421 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
422 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
423 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
424 void *irq_opaque,
425 MemoryRegion *address_space_mem,
426 MemoryRegion *address_space_io,
427 uint8_t devfn_min, int nirq,
428 const char *typename);
429 void pci_unregister_root_bus(PCIBus *bus);
430 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
431 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
432 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
433 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
434 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
435 PCIINTxRoutingNotifier notifier);
436 void pci_device_reset(PCIDevice *dev);
437
438 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
439 const char *default_model,
440 const char *default_devaddr);
441
442 PCIDevice *pci_vga_init(PCIBus *bus);
443
444 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
445 {
446 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
447 }
448 int pci_bus_num(PCIBus *s);
449 static inline int pci_dev_bus_num(const PCIDevice *dev)
450 {
451 return pci_bus_num(pci_get_bus(dev));
452 }
453
454 int pci_bus_numa_node(PCIBus *bus);
455 void pci_for_each_device(PCIBus *bus, int bus_num,
456 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
457 void *opaque);
458 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
459 void (*fn)(PCIBus *bus, PCIDevice *d,
460 void *opaque),
461 void *opaque);
462 void pci_for_each_bus_depth_first(PCIBus *bus,
463 void *(*begin)(PCIBus *bus, void *parent_state),
464 void (*end)(PCIBus *bus, void *state),
465 void *parent_state);
466 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
467
468 /* Use this wrapper when specific scan order is not required. */
469 static inline
470 void pci_for_each_bus(PCIBus *bus,
471 void (*fn)(PCIBus *bus, void *opaque),
472 void *opaque)
473 {
474 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
475 }
476
477 PCIBus *pci_device_root_bus(const PCIDevice *d);
478 const char *pci_root_bus_path(PCIDevice *dev);
479 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
480 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
481 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
482
483 void pci_device_deassert_intx(PCIDevice *dev);
484
485 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
486
487 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
488 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
489
490 static inline void
491 pci_set_byte(uint8_t *config, uint8_t val)
492 {
493 *config = val;
494 }
495
496 static inline uint8_t
497 pci_get_byte(const uint8_t *config)
498 {
499 return *config;
500 }
501
502 static inline void
503 pci_set_word(uint8_t *config, uint16_t val)
504 {
505 stw_le_p(config, val);
506 }
507
508 static inline uint16_t
509 pci_get_word(const uint8_t *config)
510 {
511 return lduw_le_p(config);
512 }
513
514 static inline void
515 pci_set_long(uint8_t *config, uint32_t val)
516 {
517 stl_le_p(config, val);
518 }
519
520 static inline uint32_t
521 pci_get_long(const uint8_t *config)
522 {
523 return ldl_le_p(config);
524 }
525
526 /*
527 * PCI capabilities and/or their fields
528 * are generally DWORD aligned only so
529 * mechanism used by pci_set/get_quad()
530 * must be tolerant to unaligned pointers
531 *
532 */
533 static inline void
534 pci_set_quad(uint8_t *config, uint64_t val)
535 {
536 stq_le_p(config, val);
537 }
538
539 static inline uint64_t
540 pci_get_quad(const uint8_t *config)
541 {
542 return ldq_le_p(config);
543 }
544
545 static inline void
546 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
547 {
548 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
549 }
550
551 static inline void
552 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
553 {
554 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
555 }
556
557 static inline void
558 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
559 {
560 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
561 }
562
563 static inline void
564 pci_config_set_class(uint8_t *pci_config, uint16_t val)
565 {
566 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
567 }
568
569 static inline void
570 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
571 {
572 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
573 }
574
575 static inline void
576 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
577 {
578 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
579 }
580
581 /*
582 * helper functions to do bit mask operation on configuration space.
583 * Just to set bit, use test-and-set and discard returned value.
584 * Just to clear bit, use test-and-clear and discard returned value.
585 * NOTE: They aren't atomic.
586 */
587 static inline uint8_t
588 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
589 {
590 uint8_t val = pci_get_byte(config);
591 pci_set_byte(config, val & ~mask);
592 return val & mask;
593 }
594
595 static inline uint8_t
596 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
597 {
598 uint8_t val = pci_get_byte(config);
599 pci_set_byte(config, val | mask);
600 return val & mask;
601 }
602
603 static inline uint16_t
604 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
605 {
606 uint16_t val = pci_get_word(config);
607 pci_set_word(config, val & ~mask);
608 return val & mask;
609 }
610
611 static inline uint16_t
612 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
613 {
614 uint16_t val = pci_get_word(config);
615 pci_set_word(config, val | mask);
616 return val & mask;
617 }
618
619 static inline uint32_t
620 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
621 {
622 uint32_t val = pci_get_long(config);
623 pci_set_long(config, val & ~mask);
624 return val & mask;
625 }
626
627 static inline uint32_t
628 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
629 {
630 uint32_t val = pci_get_long(config);
631 pci_set_long(config, val | mask);
632 return val & mask;
633 }
634
635 static inline uint64_t
636 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
637 {
638 uint64_t val = pci_get_quad(config);
639 pci_set_quad(config, val & ~mask);
640 return val & mask;
641 }
642
643 static inline uint64_t
644 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
645 {
646 uint64_t val = pci_get_quad(config);
647 pci_set_quad(config, val | mask);
648 return val & mask;
649 }
650
651 /* Access a register specified by a mask */
652 static inline void
653 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
654 {
655 uint8_t val = pci_get_byte(config);
656 uint8_t rval = reg << ctz32(mask);
657 pci_set_byte(config, (~mask & val) | (mask & rval));
658 }
659
660 static inline uint8_t
661 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
662 {
663 uint8_t val = pci_get_byte(config);
664 return (val & mask) >> ctz32(mask);
665 }
666
667 static inline void
668 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
669 {
670 uint16_t val = pci_get_word(config);
671 uint16_t rval = reg << ctz32(mask);
672 pci_set_word(config, (~mask & val) | (mask & rval));
673 }
674
675 static inline uint16_t
676 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
677 {
678 uint16_t val = pci_get_word(config);
679 return (val & mask) >> ctz32(mask);
680 }
681
682 static inline void
683 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
684 {
685 uint32_t val = pci_get_long(config);
686 uint32_t rval = reg << ctz32(mask);
687 pci_set_long(config, (~mask & val) | (mask & rval));
688 }
689
690 static inline uint32_t
691 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
692 {
693 uint32_t val = pci_get_long(config);
694 return (val & mask) >> ctz32(mask);
695 }
696
697 static inline void
698 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
699 {
700 uint64_t val = pci_get_quad(config);
701 uint64_t rval = reg << ctz32(mask);
702 pci_set_quad(config, (~mask & val) | (mask & rval));
703 }
704
705 static inline uint64_t
706 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
707 {
708 uint64_t val = pci_get_quad(config);
709 return (val & mask) >> ctz32(mask);
710 }
711
712 PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
713 const char *name);
714 PCIDevice *pci_new(int devfn, const char *name);
715 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
716
717 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
718 bool multifunction,
719 const char *name);
720 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
721
722 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
723
724 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
725 void pci_set_irq(PCIDevice *pci_dev, int level);
726
727 static inline void pci_irq_assert(PCIDevice *pci_dev)
728 {
729 pci_set_irq(pci_dev, 1);
730 }
731
732 static inline void pci_irq_deassert(PCIDevice *pci_dev)
733 {
734 pci_set_irq(pci_dev, 0);
735 }
736
737 /*
738 * FIXME: PCI does not work this way.
739 * All the callers to this method should be fixed.
740 */
741 static inline void pci_irq_pulse(PCIDevice *pci_dev)
742 {
743 pci_irq_assert(pci_dev);
744 pci_irq_deassert(pci_dev);
745 }
746
747 static inline int pci_is_express(const PCIDevice *d)
748 {
749 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
750 }
751
752 static inline int pci_is_express_downstream_port(const PCIDevice *d)
753 {
754 uint8_t type;
755
756 if (!pci_is_express(d) || !d->exp.exp_cap) {
757 return 0;
758 }
759
760 type = pcie_cap_get_type(d);
761
762 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
763 }
764
765 static inline uint32_t pci_config_size(const PCIDevice *d)
766 {
767 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
768 }
769
770 static inline uint16_t pci_get_bdf(PCIDevice *dev)
771 {
772 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
773 }
774
775 uint16_t pci_requester_id(PCIDevice *dev);
776
777 /* DMA access functions */
778 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
779 {
780 return &dev->bus_master_as;
781 }
782
783 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
784 void *buf, dma_addr_t len, DMADirection dir)
785 {
786 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
787 return 0;
788 }
789
790 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
791 void *buf, dma_addr_t len)
792 {
793 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
794 }
795
796 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
797 const void *buf, dma_addr_t len)
798 {
799 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
800 }
801
802 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
803 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
804 dma_addr_t addr) \
805 { \
806 return ld##_l##_dma(pci_get_address_space(dev), addr); \
807 } \
808 static inline void st##_s##_pci_dma(PCIDevice *dev, \
809 dma_addr_t addr, uint##_bits##_t val) \
810 { \
811 st##_s##_dma(pci_get_address_space(dev), addr, val); \
812 }
813
814 PCI_DMA_DEFINE_LDST(ub, b, 8);
815 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
816 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
817 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
818 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
819 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
820 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
821
822 #undef PCI_DMA_DEFINE_LDST
823
824 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
825 dma_addr_t *plen, DMADirection dir)
826 {
827 void *buf;
828
829 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
830 return buf;
831 }
832
833 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
834 DMADirection dir, dma_addr_t access_len)
835 {
836 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
837 }
838
839 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
840 int alloc_hint)
841 {
842 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
843 }
844
845 extern const VMStateDescription vmstate_pci_device;
846
847 #define VMSTATE_PCI_DEVICE(_field, _state) { \
848 .name = (stringify(_field)), \
849 .size = sizeof(PCIDevice), \
850 .vmsd = &vmstate_pci_device, \
851 .flags = VMS_STRUCT, \
852 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
853 }
854
855 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
856 .name = (stringify(_field)), \
857 .size = sizeof(PCIDevice), \
858 .vmsd = &vmstate_pci_device, \
859 .flags = VMS_STRUCT|VMS_POINTER, \
860 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
861 }
862
863 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
864
865 #endif