virtio-pci: Proxy for virtio-pmem
[qemu.git] / include / hw / pci / pci.h
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "hw/qdev.h"
5 #include "exec/memory.h"
6 #include "sysemu/dma.h"
7
8 /* PCI includes legacy ISA access. */
9 #include "hw/isa/isa.h"
10
11 #include "hw/pci/pcie.h"
12
13 extern bool pci_available;
14
15 /* PCI bus */
16
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
19 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
20 #define PCI_FUNC(devfn) ((devfn) & 0x07)
21 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
22 #define PCI_BUS_MAX 256
23 #define PCI_DEVFN_MAX 256
24 #define PCI_SLOT_MAX 32
25 #define PCI_FUNC_MAX 8
26
27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
28 #include "hw/pci/pci_ids.h"
29
30 /* QEMU-specific Vendor and Device ID definitions */
31
32 /* IBM (0x1014) */
33 #define PCI_DEVICE_ID_IBM_440GX 0x027f
34 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
35
36 /* Hitachi (0x1054) */
37 #define PCI_VENDOR_ID_HITACHI 0x1054
38 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
39
40 /* Apple (0x106b) */
41 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
45 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
46
47 /* Realtek (0x10ec) */
48 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
49
50 /* Xilinx (0x10ee) */
51 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
52
53 /* Marvell (0x11ab) */
54 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
55
56 /* QEMU/Bochs VGA (0x1234) */
57 #define PCI_VENDOR_ID_QEMU 0x1234
58 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
59
60 /* VMWare (0x15ad) */
61 #define PCI_VENDOR_ID_VMWARE 0x15ad
62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
69
70 /* Intel (0x8086) */
71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
72 #define PCI_DEVICE_ID_INTEL_82557 0x1229
73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
74
75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
78 #define PCI_SUBDEVICE_ID_QEMU 0x1100
79
80 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
81 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
82 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
84 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
85 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
86 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
87 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
88 #define PCI_DEVICE_ID_VIRTIO_PMEM 0x1013
89
90 #define PCI_VENDOR_ID_REDHAT 0x1b36
91 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
92 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
93 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
94 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
95 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
96 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
97 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
98 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
99 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
100 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
101 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
102 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
103 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
104 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
105 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
106 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
107
108 #define FMT_PCIBUS PRIx64
109
110 typedef uint64_t pcibus_t;
111
112 struct PCIHostDeviceAddress {
113 unsigned int domain;
114 unsigned int bus;
115 unsigned int slot;
116 unsigned int function;
117 };
118
119 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
120 uint32_t address, uint32_t data, int len);
121 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
122 uint32_t address, int len);
123 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
124 pcibus_t addr, pcibus_t size, int type);
125 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
126
127 typedef struct PCIIORegion {
128 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
129 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
130 pcibus_t size;
131 uint8_t type;
132 MemoryRegion *memory;
133 MemoryRegion *address_space;
134 } PCIIORegion;
135
136 #define PCI_ROM_SLOT 6
137 #define PCI_NUM_REGIONS 7
138
139 enum {
140 QEMU_PCI_VGA_MEM,
141 QEMU_PCI_VGA_IO_LO,
142 QEMU_PCI_VGA_IO_HI,
143 QEMU_PCI_VGA_NUM_REGIONS,
144 };
145
146 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
147 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
148 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
149 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
150 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
151 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
152
153 #include "hw/pci/pci_regs.h"
154
155 /* PCI HEADER_TYPE */
156 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
157
158 /* Size of the standard PCI config header */
159 #define PCI_CONFIG_HEADER_SIZE 0x40
160 /* Size of the standard PCI config space */
161 #define PCI_CONFIG_SPACE_SIZE 0x100
162 /* Size of the standard PCIe config space: 4KB */
163 #define PCIE_CONFIG_SPACE_SIZE 0x1000
164
165 #define PCI_NUM_PINS 4 /* A-D */
166
167 /* Bits in cap_present field. */
168 enum {
169 QEMU_PCI_CAP_MSI = 0x1,
170 QEMU_PCI_CAP_MSIX = 0x2,
171 QEMU_PCI_CAP_EXPRESS = 0x4,
172
173 /* multifunction capable device */
174 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
175 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
176
177 /* command register SERR bit enabled */
178 #define QEMU_PCI_CAP_SERR_BITNR 4
179 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
180 /* Standard hot plug controller. */
181 #define QEMU_PCI_SHPC_BITNR 5
182 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
183 #define QEMU_PCI_SLOTID_BITNR 6
184 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
185 /* PCI Express capability - Power Controller Present */
186 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
187 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
188 /* Link active status in endpoint capability is always set */
189 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
190 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
191 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
192 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
193 };
194
195 #define TYPE_PCI_DEVICE "pci-device"
196 #define PCI_DEVICE(obj) \
197 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
198 #define PCI_DEVICE_CLASS(klass) \
199 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
200 #define PCI_DEVICE_GET_CLASS(obj) \
201 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
202
203 /* Implemented by devices that can be plugged on PCI Express buses */
204 #define INTERFACE_PCIE_DEVICE "pci-express-device"
205
206 /* Implemented by devices that can be plugged on Conventional PCI buses */
207 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
208
209 typedef struct PCIINTxRoute {
210 enum {
211 PCI_INTX_ENABLED,
212 PCI_INTX_INVERTED,
213 PCI_INTX_DISABLED,
214 } mode;
215 int irq;
216 } PCIINTxRoute;
217
218 typedef struct PCIDeviceClass {
219 DeviceClass parent_class;
220
221 void (*realize)(PCIDevice *dev, Error **errp);
222 PCIUnregisterFunc *exit;
223 PCIConfigReadFunc *config_read;
224 PCIConfigWriteFunc *config_write;
225
226 uint16_t vendor_id;
227 uint16_t device_id;
228 uint8_t revision;
229 uint16_t class_id;
230 uint16_t subsystem_vendor_id; /* only for header type = 0 */
231 uint16_t subsystem_id; /* only for header type = 0 */
232
233 /*
234 * pci-to-pci bridge or normal device.
235 * This doesn't mean pci host switch.
236 * When card bus bridge is supported, this would be enhanced.
237 */
238 bool is_bridge;
239
240 /* rom bar */
241 const char *romfile;
242 } PCIDeviceClass;
243
244 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
245 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
246 MSIMessage msg);
247 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
248 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
249 unsigned int vector_start,
250 unsigned int vector_end);
251
252 enum PCIReqIDType {
253 PCI_REQ_ID_INVALID = 0,
254 PCI_REQ_ID_BDF,
255 PCI_REQ_ID_SECONDARY_BUS,
256 PCI_REQ_ID_MAX,
257 };
258 typedef enum PCIReqIDType PCIReqIDType;
259
260 struct PCIReqIDCache {
261 PCIDevice *dev;
262 PCIReqIDType type;
263 };
264 typedef struct PCIReqIDCache PCIReqIDCache;
265
266 struct PCIDevice {
267 DeviceState qdev;
268
269 /* PCI config space */
270 uint8_t *config;
271
272 /* Used to enable config checks on load. Note that writable bits are
273 * never checked even if set in cmask. */
274 uint8_t *cmask;
275
276 /* Used to implement R/W bytes */
277 uint8_t *wmask;
278
279 /* Used to implement RW1C(Write 1 to Clear) bytes */
280 uint8_t *w1cmask;
281
282 /* Used to allocate config space for capabilities. */
283 uint8_t *used;
284
285 /* the following fields are read only */
286 int32_t devfn;
287 /* Cached device to fetch requester ID from, to avoid the PCI
288 * tree walking every time we invoke PCI request (e.g.,
289 * MSI). For conventional PCI root complex, this field is
290 * meaningless. */
291 PCIReqIDCache requester_id_cache;
292 char name[64];
293 PCIIORegion io_regions[PCI_NUM_REGIONS];
294 AddressSpace bus_master_as;
295 MemoryRegion bus_master_container_region;
296 MemoryRegion bus_master_enable_region;
297
298 /* do not access the following fields */
299 PCIConfigReadFunc *config_read;
300 PCIConfigWriteFunc *config_write;
301
302 /* Legacy PCI VGA regions */
303 MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
304 bool has_vga;
305
306 /* Current IRQ levels. Used internally by the generic PCI code. */
307 uint8_t irq_state;
308
309 /* Capability bits */
310 uint32_t cap_present;
311
312 /* Offset of MSI-X capability in config space */
313 uint8_t msix_cap;
314
315 /* MSI-X entries */
316 int msix_entries_nr;
317
318 /* Space to store MSIX table & pending bit array */
319 uint8_t *msix_table;
320 uint8_t *msix_pba;
321 /* MemoryRegion container for msix exclusive BAR setup */
322 MemoryRegion msix_exclusive_bar;
323 /* Memory Regions for MSIX table and pending bit entries. */
324 MemoryRegion msix_table_mmio;
325 MemoryRegion msix_pba_mmio;
326 /* Reference-count for entries actually in use by driver. */
327 unsigned *msix_entry_used;
328 /* MSIX function mask set or MSIX disabled */
329 bool msix_function_masked;
330 /* Version id needed for VMState */
331 int32_t version_id;
332
333 /* Offset of MSI capability in config space */
334 uint8_t msi_cap;
335
336 /* PCI Express */
337 PCIExpressDevice exp;
338
339 /* SHPC */
340 SHPCDevice *shpc;
341
342 /* Location of option rom */
343 char *romfile;
344 bool has_rom;
345 MemoryRegion rom;
346 uint32_t rom_bar;
347
348 /* INTx routing notifier */
349 PCIINTxRoutingNotifier intx_routing_notifier;
350
351 /* MSI-X notifiers */
352 MSIVectorUseNotifier msix_vector_use_notifier;
353 MSIVectorReleaseNotifier msix_vector_release_notifier;
354 MSIVectorPollNotifier msix_vector_poll_notifier;
355 };
356
357 void pci_register_bar(PCIDevice *pci_dev, int region_num,
358 uint8_t attr, MemoryRegion *memory);
359 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
360 MemoryRegion *io_lo, MemoryRegion *io_hi);
361 void pci_unregister_vga(PCIDevice *pci_dev);
362 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
363
364 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
365 uint8_t offset, uint8_t size,
366 Error **errp);
367
368 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
369
370 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
371
372
373 uint32_t pci_default_read_config(PCIDevice *d,
374 uint32_t address, int len);
375 void pci_default_write_config(PCIDevice *d,
376 uint32_t address, uint32_t val, int len);
377 void pci_device_save(PCIDevice *s, QEMUFile *f);
378 int pci_device_load(PCIDevice *s, QEMUFile *f);
379 MemoryRegion *pci_address_space(PCIDevice *dev);
380 MemoryRegion *pci_address_space_io(PCIDevice *dev);
381
382 /*
383 * Should not normally be used by devices. For use by sPAPR target
384 * where QEMU emulates firmware.
385 */
386 int pci_bar(PCIDevice *d, int reg);
387
388 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
389 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
390 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
391
392 #define TYPE_PCI_BUS "PCI"
393 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
394 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
395 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
396 #define TYPE_PCIE_BUS "PCIE"
397
398 bool pci_bus_is_express(PCIBus *bus);
399
400 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
401 const char *name,
402 MemoryRegion *address_space_mem,
403 MemoryRegion *address_space_io,
404 uint8_t devfn_min, const char *typename);
405 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
406 MemoryRegion *address_space_mem,
407 MemoryRegion *address_space_io,
408 uint8_t devfn_min, const char *typename);
409 void pci_root_bus_cleanup(PCIBus *bus);
410 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
411 void *irq_opaque, int nirq);
412 void pci_bus_irqs_cleanup(PCIBus *bus);
413 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
414 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
415 static inline int pci_swizzle(int slot, int pin)
416 {
417 return (slot + pin) % PCI_NUM_PINS;
418 }
419 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
420 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
421 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
422 void *irq_opaque,
423 MemoryRegion *address_space_mem,
424 MemoryRegion *address_space_io,
425 uint8_t devfn_min, int nirq,
426 const char *typename);
427 void pci_unregister_root_bus(PCIBus *bus);
428 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
429 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
430 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
431 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
432 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
433 PCIINTxRoutingNotifier notifier);
434 void pci_device_reset(PCIDevice *dev);
435
436 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
437 const char *default_model,
438 const char *default_devaddr);
439
440 PCIDevice *pci_vga_init(PCIBus *bus);
441
442 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
443 {
444 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
445 }
446 int pci_bus_num(PCIBus *s);
447 static inline int pci_dev_bus_num(const PCIDevice *dev)
448 {
449 return pci_bus_num(pci_get_bus(dev));
450 }
451
452 int pci_bus_numa_node(PCIBus *bus);
453 void pci_for_each_device(PCIBus *bus, int bus_num,
454 void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
455 void *opaque);
456 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
457 void (*fn)(PCIBus *bus, PCIDevice *d,
458 void *opaque),
459 void *opaque);
460 void pci_for_each_bus_depth_first(PCIBus *bus,
461 void *(*begin)(PCIBus *bus, void *parent_state),
462 void (*end)(PCIBus *bus, void *state),
463 void *parent_state);
464 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
465
466 /* Use this wrapper when specific scan order is not required. */
467 static inline
468 void pci_for_each_bus(PCIBus *bus,
469 void (*fn)(PCIBus *bus, void *opaque),
470 void *opaque)
471 {
472 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
473 }
474
475 PCIBus *pci_device_root_bus(const PCIDevice *d);
476 const char *pci_root_bus_path(PCIDevice *dev);
477 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
478 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
479 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
480
481 void pci_device_deassert_intx(PCIDevice *dev);
482
483 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
484
485 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
486 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
487
488 static inline void
489 pci_set_byte(uint8_t *config, uint8_t val)
490 {
491 *config = val;
492 }
493
494 static inline uint8_t
495 pci_get_byte(const uint8_t *config)
496 {
497 return *config;
498 }
499
500 static inline void
501 pci_set_word(uint8_t *config, uint16_t val)
502 {
503 stw_le_p(config, val);
504 }
505
506 static inline uint16_t
507 pci_get_word(const uint8_t *config)
508 {
509 return lduw_le_p(config);
510 }
511
512 static inline void
513 pci_set_long(uint8_t *config, uint32_t val)
514 {
515 stl_le_p(config, val);
516 }
517
518 static inline uint32_t
519 pci_get_long(const uint8_t *config)
520 {
521 return ldl_le_p(config);
522 }
523
524 /*
525 * PCI capabilities and/or their fields
526 * are generally DWORD aligned only so
527 * mechanism used by pci_set/get_quad()
528 * must be tolerant to unaligned pointers
529 *
530 */
531 static inline void
532 pci_set_quad(uint8_t *config, uint64_t val)
533 {
534 stq_le_p(config, val);
535 }
536
537 static inline uint64_t
538 pci_get_quad(const uint8_t *config)
539 {
540 return ldq_le_p(config);
541 }
542
543 static inline void
544 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
545 {
546 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
547 }
548
549 static inline void
550 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
551 {
552 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
553 }
554
555 static inline void
556 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
557 {
558 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
559 }
560
561 static inline void
562 pci_config_set_class(uint8_t *pci_config, uint16_t val)
563 {
564 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
565 }
566
567 static inline void
568 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
569 {
570 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
571 }
572
573 static inline void
574 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
575 {
576 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
577 }
578
579 /*
580 * helper functions to do bit mask operation on configuration space.
581 * Just to set bit, use test-and-set and discard returned value.
582 * Just to clear bit, use test-and-clear and discard returned value.
583 * NOTE: They aren't atomic.
584 */
585 static inline uint8_t
586 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
587 {
588 uint8_t val = pci_get_byte(config);
589 pci_set_byte(config, val & ~mask);
590 return val & mask;
591 }
592
593 static inline uint8_t
594 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
595 {
596 uint8_t val = pci_get_byte(config);
597 pci_set_byte(config, val | mask);
598 return val & mask;
599 }
600
601 static inline uint16_t
602 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
603 {
604 uint16_t val = pci_get_word(config);
605 pci_set_word(config, val & ~mask);
606 return val & mask;
607 }
608
609 static inline uint16_t
610 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
611 {
612 uint16_t val = pci_get_word(config);
613 pci_set_word(config, val | mask);
614 return val & mask;
615 }
616
617 static inline uint32_t
618 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
619 {
620 uint32_t val = pci_get_long(config);
621 pci_set_long(config, val & ~mask);
622 return val & mask;
623 }
624
625 static inline uint32_t
626 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
627 {
628 uint32_t val = pci_get_long(config);
629 pci_set_long(config, val | mask);
630 return val & mask;
631 }
632
633 static inline uint64_t
634 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
635 {
636 uint64_t val = pci_get_quad(config);
637 pci_set_quad(config, val & ~mask);
638 return val & mask;
639 }
640
641 static inline uint64_t
642 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
643 {
644 uint64_t val = pci_get_quad(config);
645 pci_set_quad(config, val | mask);
646 return val & mask;
647 }
648
649 /* Access a register specified by a mask */
650 static inline void
651 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
652 {
653 uint8_t val = pci_get_byte(config);
654 uint8_t rval = reg << ctz32(mask);
655 pci_set_byte(config, (~mask & val) | (mask & rval));
656 }
657
658 static inline uint8_t
659 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
660 {
661 uint8_t val = pci_get_byte(config);
662 return (val & mask) >> ctz32(mask);
663 }
664
665 static inline void
666 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
667 {
668 uint16_t val = pci_get_word(config);
669 uint16_t rval = reg << ctz32(mask);
670 pci_set_word(config, (~mask & val) | (mask & rval));
671 }
672
673 static inline uint16_t
674 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
675 {
676 uint16_t val = pci_get_word(config);
677 return (val & mask) >> ctz32(mask);
678 }
679
680 static inline void
681 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
682 {
683 uint32_t val = pci_get_long(config);
684 uint32_t rval = reg << ctz32(mask);
685 pci_set_long(config, (~mask & val) | (mask & rval));
686 }
687
688 static inline uint32_t
689 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
690 {
691 uint32_t val = pci_get_long(config);
692 return (val & mask) >> ctz32(mask);
693 }
694
695 static inline void
696 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
697 {
698 uint64_t val = pci_get_quad(config);
699 uint64_t rval = reg << ctz32(mask);
700 pci_set_quad(config, (~mask & val) | (mask & rval));
701 }
702
703 static inline uint64_t
704 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
705 {
706 uint64_t val = pci_get_quad(config);
707 return (val & mask) >> ctz32(mask);
708 }
709
710 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
711 const char *name);
712 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
713 bool multifunction,
714 const char *name);
715 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
716 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
717
718 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
719
720 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
721 void pci_set_irq(PCIDevice *pci_dev, int level);
722
723 static inline void pci_irq_assert(PCIDevice *pci_dev)
724 {
725 pci_set_irq(pci_dev, 1);
726 }
727
728 static inline void pci_irq_deassert(PCIDevice *pci_dev)
729 {
730 pci_set_irq(pci_dev, 0);
731 }
732
733 /*
734 * FIXME: PCI does not work this way.
735 * All the callers to this method should be fixed.
736 */
737 static inline void pci_irq_pulse(PCIDevice *pci_dev)
738 {
739 pci_irq_assert(pci_dev);
740 pci_irq_deassert(pci_dev);
741 }
742
743 static inline int pci_is_express(const PCIDevice *d)
744 {
745 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
746 }
747
748 static inline int pci_is_express_downstream_port(const PCIDevice *d)
749 {
750 uint8_t type;
751
752 if (!pci_is_express(d) || !d->exp.exp_cap) {
753 return 0;
754 }
755
756 type = pcie_cap_get_type(d);
757
758 return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
759 }
760
761 static inline uint32_t pci_config_size(const PCIDevice *d)
762 {
763 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
764 }
765
766 static inline uint16_t pci_get_bdf(PCIDevice *dev)
767 {
768 return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
769 }
770
771 uint16_t pci_requester_id(PCIDevice *dev);
772
773 /* DMA access functions */
774 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
775 {
776 return &dev->bus_master_as;
777 }
778
779 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
780 void *buf, dma_addr_t len, DMADirection dir)
781 {
782 dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
783 return 0;
784 }
785
786 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
787 void *buf, dma_addr_t len)
788 {
789 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
790 }
791
792 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
793 const void *buf, dma_addr_t len)
794 {
795 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
796 }
797
798 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
799 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
800 dma_addr_t addr) \
801 { \
802 return ld##_l##_dma(pci_get_address_space(dev), addr); \
803 } \
804 static inline void st##_s##_pci_dma(PCIDevice *dev, \
805 dma_addr_t addr, uint##_bits##_t val) \
806 { \
807 st##_s##_dma(pci_get_address_space(dev), addr, val); \
808 }
809
810 PCI_DMA_DEFINE_LDST(ub, b, 8);
811 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
812 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
813 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
814 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
815 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
816 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
817
818 #undef PCI_DMA_DEFINE_LDST
819
820 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
821 dma_addr_t *plen, DMADirection dir)
822 {
823 void *buf;
824
825 buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
826 return buf;
827 }
828
829 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
830 DMADirection dir, dma_addr_t access_len)
831 {
832 dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
833 }
834
835 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
836 int alloc_hint)
837 {
838 qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
839 }
840
841 extern const VMStateDescription vmstate_pci_device;
842
843 #define VMSTATE_PCI_DEVICE(_field, _state) { \
844 .name = (stringify(_field)), \
845 .size = sizeof(PCIDevice), \
846 .vmsd = &vmstate_pci_device, \
847 .flags = VMS_STRUCT, \
848 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
849 }
850
851 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
852 .name = (stringify(_field)), \
853 .size = sizeof(PCIDevice), \
854 .vmsd = &vmstate_pci_device, \
855 .flags = VMS_STRUCT|VMS_POINTER, \
856 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
857 }
858
859 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
860
861 #endif