Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210511...
[qemu.git] / include / hw / pci / pcie.h
1 /*
2 * pcie.h
3 *
4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #ifndef QEMU_PCIE_H
22 #define QEMU_PCIE_H
23
24 #include "hw/pci/pci_regs.h"
25 #include "hw/pci/pcie_regs.h"
26 #include "hw/pci/pcie_aer.h"
27 #include "hw/hotplug.h"
28
29 typedef enum {
30 /* for attention and power indicator */
31 PCI_EXP_HP_IND_RESERVED = PCI_EXP_SLTCTL_IND_RESERVED,
32 PCI_EXP_HP_IND_ON = PCI_EXP_SLTCTL_IND_ON,
33 PCI_EXP_HP_IND_BLINK = PCI_EXP_SLTCTL_IND_BLINK,
34 PCI_EXP_HP_IND_OFF = PCI_EXP_SLTCTL_IND_OFF,
35 } PCIExpressIndicator;
36
37 typedef enum {
38 /* these bits must match the bits in Slot Control/Status registers.
39 * PCI_EXP_HP_EV_xxx = PCI_EXP_SLTCTL_xxxE = PCI_EXP_SLTSTA_xxx
40 *
41 * Not all the bits of slot control register match with the ones of
42 * slot status. Not some bits of slot status register is used to
43 * show status, not to report event occurrence.
44 * So such bits must be masked out when checking the software
45 * notification condition.
46 */
47 PCI_EXP_HP_EV_ABP = PCI_EXP_SLTCTL_ABPE,
48 /* attention button pressed */
49 PCI_EXP_HP_EV_PDC = PCI_EXP_SLTCTL_PDCE,
50 /* presence detect changed */
51 PCI_EXP_HP_EV_CCI = PCI_EXP_SLTCTL_CCIE,
52 /* command completed */
53
54 PCI_EXP_HP_EV_SUPPORTED = PCI_EXP_HP_EV_ABP |
55 PCI_EXP_HP_EV_PDC |
56 PCI_EXP_HP_EV_CCI,
57 /* supported event mask */
58
59 /* events not listed aren't supported */
60 } PCIExpressHotPlugEvent;
61
62 struct PCIExpressDevice {
63 /* Offset of express capability in config space */
64 uint8_t exp_cap;
65 /* Offset of Power Management capability in config space */
66 uint8_t pm_cap;
67
68 /* SLOT */
69 bool hpev_notified; /* Logical AND of conditions for hot plug event.
70 Following 6.7.3.4:
71 Software Notification of Hot-Plug Events, an interrupt
72 is sent whenever the logical and of these conditions
73 transitions from false to true. */
74
75 /* AER */
76 uint16_t aer_cap;
77 PCIEAERLog aer_log;
78
79 /* Offset of ATS capability in config space */
80 uint16_t ats_cap;
81
82 /* ACS */
83 uint16_t acs_cap;
84 };
85
86 #define COMPAT_PROP_PCP "power_controller_present"
87
88 /* PCI express capability helper functions */
89 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type,
90 uint8_t port, Error **errp);
91 int pcie_cap_v1_init(PCIDevice *dev, uint8_t offset,
92 uint8_t type, uint8_t port);
93 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset);
94 void pcie_cap_exit(PCIDevice *dev);
95 int pcie_endpoint_cap_v1_init(PCIDevice *dev, uint8_t offset);
96 void pcie_cap_v1_exit(PCIDevice *dev);
97 uint8_t pcie_cap_get_type(const PCIDevice *dev);
98 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector);
99 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev);
100
101 void pcie_cap_deverr_init(PCIDevice *dev);
102 void pcie_cap_deverr_reset(PCIDevice *dev);
103
104 void pcie_cap_lnkctl_init(PCIDevice *dev);
105 void pcie_cap_lnkctl_reset(PCIDevice *dev);
106
107 void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s);
108 void pcie_cap_slot_reset(PCIDevice *dev);
109 void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta);
110 void pcie_cap_slot_write_config(PCIDevice *dev,
111 uint16_t old_slt_ctl, uint16_t old_slt_sta,
112 uint32_t addr, uint32_t val, int len);
113 int pcie_cap_slot_post_load(void *opaque, int version_id);
114 void pcie_cap_slot_push_attention_button(PCIDevice *dev);
115
116 void pcie_cap_root_init(PCIDevice *dev);
117 void pcie_cap_root_reset(PCIDevice *dev);
118
119 void pcie_cap_flr_init(PCIDevice *dev);
120 void pcie_cap_flr_write_config(PCIDevice *dev,
121 uint32_t addr, uint32_t val, int len);
122
123 /* ARI forwarding capability and control */
124 void pcie_cap_arifwd_init(PCIDevice *dev);
125 void pcie_cap_arifwd_reset(PCIDevice *dev);
126 bool pcie_cap_is_arifwd_enabled(const PCIDevice *dev);
127
128 /* PCI express extended capability helper functions */
129 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id);
130 void pcie_add_capability(PCIDevice *dev,
131 uint16_t cap_id, uint8_t cap_ver,
132 uint16_t offset, uint16_t size);
133 void pcie_sync_bridge_lnk(PCIDevice *dev);
134
135 void pcie_acs_init(PCIDevice *dev, uint16_t offset);
136 void pcie_acs_reset(PCIDevice *dev);
137
138 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn);
139 void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_num);
140 void pcie_ats_init(PCIDevice *dev, uint16_t offset, bool aligned);
141
142 void pcie_cap_slot_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
143 Error **errp);
144 void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
145 Error **errp);
146 void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
147 Error **errp);
148 void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
149 DeviceState *dev, Error **errp);
150 #endif /* QEMU_PCIE_H */