block/export: Add query-block-exports
[qemu.git] / include / hw / ppc / mac_dbdma.h
1 /*
2 * Copyright (c) 2009 Laurent Vivier
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23 #ifndef HW_MAC_DBDMA_H
24 #define HW_MAC_DBDMA_H
25
26 #include "exec/memory.h"
27 #include "qemu/iov.h"
28 #include "sysemu/dma.h"
29 #include "hw/sysbus.h"
30 #include "qom/object.h"
31
32 typedef struct DBDMA_io DBDMA_io;
33
34 typedef void (*DBDMA_flush)(DBDMA_io *io);
35 typedef void (*DBDMA_rw)(DBDMA_io *io);
36 typedef void (*DBDMA_end)(DBDMA_io *io);
37 struct DBDMA_io {
38 void *opaque;
39 void *channel;
40 hwaddr addr;
41 int len;
42 int is_last;
43 int is_dma_out;
44 DBDMA_end dma_end;
45 /* DMA is in progress, don't start another one */
46 bool processing;
47 /* DMA request */
48 void *dma_mem;
49 dma_addr_t dma_len;
50 DMADirection dir;
51 };
52
53 /*
54 * DBDMA control/status registers. All little-endian.
55 */
56
57 #define DBDMA_CONTROL 0x00
58 #define DBDMA_STATUS 0x01
59 #define DBDMA_CMDPTR_HI 0x02
60 #define DBDMA_CMDPTR_LO 0x03
61 #define DBDMA_INTR_SEL 0x04
62 #define DBDMA_BRANCH_SEL 0x05
63 #define DBDMA_WAIT_SEL 0x06
64 #define DBDMA_XFER_MODE 0x07
65 #define DBDMA_DATA2PTR_HI 0x08
66 #define DBDMA_DATA2PTR_LO 0x09
67 #define DBDMA_RES1 0x0A
68 #define DBDMA_ADDRESS_HI 0x0B
69 #define DBDMA_BRANCH_ADDR_HI 0x0C
70 #define DBDMA_RES2 0x0D
71 #define DBDMA_RES3 0x0E
72 #define DBDMA_RES4 0x0F
73
74 #define DBDMA_REGS 16
75 #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t))
76
77 #define DBDMA_CHANNEL_SHIFT 7
78 #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT)
79
80 #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT)
81
82 /* Bits in control and status registers */
83
84 #define RUN 0x8000
85 #define PAUSE 0x4000
86 #define FLUSH 0x2000
87 #define WAKE 0x1000
88 #define DEAD 0x0800
89 #define ACTIVE 0x0400
90 #define BT 0x0100
91 #define DEVSTAT 0x00ff
92
93 /*
94 * DBDMA command structure. These fields are all little-endian!
95 */
96
97 typedef struct dbdma_cmd {
98 uint16_t req_count; /* requested byte transfer count */
99 uint16_t command; /* command word (has bit-fields) */
100 uint32_t phy_addr; /* physical data address */
101 uint32_t cmd_dep; /* command-dependent field */
102 uint16_t res_count; /* residual count after completion */
103 uint16_t xfer_status; /* transfer status */
104 } dbdma_cmd;
105
106 /* DBDMA command values in command field */
107
108 #define COMMAND_MASK 0xf000
109 #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */
110 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
111 #define INPUT_MORE 0x2000 /* transfer stream data to memory */
112 #define INPUT_LAST 0x3000 /* ditto, expect end marker */
113 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
114 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
115 #define DBDMA_NOP 0x6000 /* do nothing */
116 #define DBDMA_STOP 0x7000 /* suspend processing */
117
118 /* Key values in command field */
119
120 #define KEY_MASK 0x0700
121 #define KEY_STREAM0 0x0000 /* usual data stream */
122 #define KEY_STREAM1 0x0100 /* control/status stream */
123 #define KEY_STREAM2 0x0200 /* device-dependent stream */
124 #define KEY_STREAM3 0x0300 /* device-dependent stream */
125 #define KEY_STREAM4 0x0400 /* reserved */
126 #define KEY_REGS 0x0500 /* device register space */
127 #define KEY_SYSTEM 0x0600 /* system memory-mapped space */
128 #define KEY_DEVICE 0x0700 /* device memory-mapped space */
129
130 /* Interrupt control values in command field */
131
132 #define INTR_MASK 0x0030
133 #define INTR_NEVER 0x0000 /* don't interrupt */
134 #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */
135 #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */
136 #define INTR_ALWAYS 0x0030 /* always interrupt */
137
138 /* Branch control values in command field */
139
140 #define BR_MASK 0x000c
141 #define BR_NEVER 0x0000 /* don't branch */
142 #define BR_IFSET 0x0004 /* branch if condition bit is 1 */
143 #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */
144 #define BR_ALWAYS 0x000c /* always branch */
145
146 /* Wait control values in command field */
147
148 #define WAIT_MASK 0x0003
149 #define WAIT_NEVER 0x0000 /* don't wait */
150 #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */
151 #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */
152 #define WAIT_ALWAYS 0x0003 /* always wait */
153
154 typedef struct DBDMA_channel {
155 int channel;
156 uint32_t regs[DBDMA_REGS];
157 qemu_irq irq;
158 DBDMA_io io;
159 DBDMA_rw rw;
160 DBDMA_flush flush;
161 dbdma_cmd current;
162 } DBDMA_channel;
163
164 struct DBDMAState {
165 SysBusDevice parent_obj;
166
167 MemoryRegion mem;
168 DBDMA_channel channels[DBDMA_CHANNELS];
169 QEMUBH *bh;
170 };
171 typedef struct DBDMAState DBDMAState;
172
173 /* Externally callable functions */
174
175 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
176 DBDMA_rw rw, DBDMA_flush flush,
177 void *opaque);
178 void DBDMA_kick(DBDMAState *dbdma);
179
180 #define TYPE_MAC_DBDMA "mac-dbdma"
181 OBJECT_DECLARE_SIMPLE_TYPE(DBDMAState, MAC_DBDMA)
182
183 #endif