ppc/pnv: add memory regions for the ICP registers
[qemu.git] / include / hw / ppc / pnv.h
1 /*
2 * QEMU PowerPC PowerNV various definitions
3 *
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef _PPC_PNV_H
20 #define _PPC_PNV_H
21
22 #include "hw/boards.h"
23 #include "hw/sysbus.h"
24 #include "hw/ppc/pnv_lpc.h"
25
26 #define TYPE_PNV_CHIP "powernv-chip"
27 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
28 #define PNV_CHIP_CLASS(klass) \
29 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
30 #define PNV_CHIP_GET_CLASS(obj) \
31 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
32
33 typedef enum PnvChipType {
34 PNV_CHIP_POWER8E, /* AKA Murano (default) */
35 PNV_CHIP_POWER8, /* AKA Venice */
36 PNV_CHIP_POWER8NVL, /* AKA Naples */
37 PNV_CHIP_POWER9, /* AKA Nimbus */
38 } PnvChipType;
39
40 typedef struct PnvChip {
41 /*< private >*/
42 SysBusDevice parent_obj;
43
44 /*< public >*/
45 uint32_t chip_id;
46 uint64_t ram_start;
47 uint64_t ram_size;
48
49 uint32_t nr_cores;
50 uint64_t cores_mask;
51 void *cores;
52
53 hwaddr xscom_base;
54 MemoryRegion xscom_mmio;
55 MemoryRegion xscom;
56 AddressSpace xscom_as;
57 MemoryRegion icp_mmio;
58
59 PnvLpcController lpc;
60 } PnvChip;
61
62 typedef struct PnvChipClass {
63 /*< private >*/
64 SysBusDeviceClass parent_class;
65
66 /*< public >*/
67 const char *cpu_model;
68 PnvChipType chip_type;
69 uint64_t chip_cfam_id;
70 uint64_t cores_mask;
71
72 hwaddr xscom_base;
73 hwaddr xscom_core_base;
74
75 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
76 } PnvChipClass;
77
78 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
79 #define PNV_CHIP_POWER8E(obj) \
80 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
81
82 #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8"
83 #define PNV_CHIP_POWER8(obj) \
84 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
85
86 #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL"
87 #define PNV_CHIP_POWER8NVL(obj) \
88 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
89
90 #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9"
91 #define PNV_CHIP_POWER9(obj) \
92 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
93
94 /*
95 * This generates a HW chip id depending on an index, as found on a
96 * two socket system with dual chip modules :
97 *
98 * 0x0, 0x1, 0x10, 0x11
99 *
100 * 4 chips should be the maximum
101 *
102 * TODO: use a machine property to define the chip ids
103 */
104 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
105
106 /*
107 * Converts back a HW chip id to an index. This is useful to calculate
108 * the MMIO addresses of some controllers which depend on the chip id.
109 */
110 #define PNV_CHIP_INDEX(chip) \
111 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
112
113 #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
114 #define POWERNV_MACHINE(obj) \
115 OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
116
117 typedef struct PnvMachineState {
118 /*< private >*/
119 MachineState parent_obj;
120
121 uint32_t initrd_base;
122 long initrd_size;
123
124 uint32_t num_chips;
125 PnvChip **chips;
126
127 ISABus *isa_bus;
128 } PnvMachineState;
129
130 #define PNV_FDT_ADDR 0x01000000
131 #define PNV_TIMEBASE_FREQ 512000000ULL
132
133 /*
134 * POWER8 MMIO base addresses
135 */
136 #define PNV_XSCOM_SIZE 0x800000000ull
137 #define PNV_XSCOM_BASE(chip) \
138 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
139
140 /*
141 * XSCOM 0x20109CA defines the ICP BAR:
142 *
143 * 0:29 : bits 14 to 43 of address to define 1 MB region.
144 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
145 * 31:63 : Constant 0
146 *
147 * Usually defined as :
148 *
149 * 0xffffe00200000000 -> 0x0003ffff80000000
150 * 0xffffe00600000000 -> 0x0003ffff80100000
151 * 0xffffe02200000000 -> 0x0003ffff80800000
152 * 0xffffe02600000000 -> 0x0003ffff80900000
153 */
154 #define PNV_ICP_SIZE 0x0000000000100000ull
155 #define PNV_ICP_BASE(chip) \
156 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
157
158 #endif /* _PPC_PNV_H */