block/export: Add query-block-exports
[qemu.git] / include / hw / ppc / pnv.h
1 /*
2 * QEMU PowerPC PowerNV various definitions
3 *
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_PNV_H
21 #define PPC_PNV_H
22
23 #include "hw/boards.h"
24 #include "hw/sysbus.h"
25 #include "hw/ipmi/ipmi.h"
26 #include "hw/ppc/pnv_lpc.h"
27 #include "hw/ppc/pnv_pnor.h"
28 #include "hw/ppc/pnv_psi.h"
29 #include "hw/ppc/pnv_occ.h"
30 #include "hw/ppc/pnv_homer.h"
31 #include "hw/ppc/pnv_xive.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/pci-host/pnv_phb3.h"
34 #include "hw/pci-host/pnv_phb4.h"
35 #include "qom/object.h"
36
37 #define TYPE_PNV_CHIP "pnv-chip"
38 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
39 PNV_CHIP)
40
41 struct PnvChip {
42 /*< private >*/
43 SysBusDevice parent_obj;
44
45 /*< public >*/
46 uint32_t chip_id;
47 uint64_t ram_start;
48 uint64_t ram_size;
49
50 uint32_t nr_cores;
51 uint32_t nr_threads;
52 uint64_t cores_mask;
53 PnvCore **cores;
54
55 uint32_t num_phbs;
56
57 MemoryRegion xscom_mmio;
58 MemoryRegion xscom;
59 AddressSpace xscom_as;
60
61 gchar *dt_isa_nodename;
62 };
63
64 #define TYPE_PNV8_CHIP "pnv8-chip"
65 typedef struct Pnv8Chip Pnv8Chip;
66 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
67 TYPE_PNV8_CHIP)
68
69 struct Pnv8Chip {
70 /*< private >*/
71 PnvChip parent_obj;
72
73 /*< public >*/
74 MemoryRegion icp_mmio;
75
76 PnvLpcController lpc;
77 Pnv8Psi psi;
78 PnvOCC occ;
79 PnvHomer homer;
80
81 #define PNV8_CHIP_PHB3_MAX 4
82 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
83
84 XICSFabric *xics;
85 };
86
87 #define TYPE_PNV9_CHIP "pnv9-chip"
88 typedef struct Pnv9Chip Pnv9Chip;
89 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
90 TYPE_PNV9_CHIP)
91
92 struct Pnv9Chip {
93 /*< private >*/
94 PnvChip parent_obj;
95
96 /*< public >*/
97 PnvXive xive;
98 Pnv9Psi psi;
99 PnvLpcController lpc;
100 PnvOCC occ;
101 PnvHomer homer;
102
103 uint32_t nr_quads;
104 PnvQuad *quads;
105
106 #define PNV9_CHIP_MAX_PEC 3
107 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
108 };
109
110 /*
111 * A SMT8 fused core is a pair of SMT4 cores.
112 */
113 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
114 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
115
116 #define TYPE_PNV10_CHIP "pnv10-chip"
117 typedef struct Pnv10Chip Pnv10Chip;
118 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
119 TYPE_PNV10_CHIP)
120
121 struct Pnv10Chip {
122 /*< private >*/
123 PnvChip parent_obj;
124
125 /*< public >*/
126 Pnv9Psi psi;
127 PnvLpcController lpc;
128 };
129
130 struct PnvChipClass {
131 /*< private >*/
132 SysBusDeviceClass parent_class;
133
134 /*< public >*/
135 uint64_t chip_cfam_id;
136 uint64_t cores_mask;
137 uint32_t num_phbs;
138
139 DeviceRealize parent_realize;
140
141 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
142 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
143 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
144 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
145 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
146 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
147 void (*dt_populate)(PnvChip *chip, void *fdt);
148 void (*pic_print_info)(PnvChip *chip, Monitor *mon);
149 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
150 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
151 };
152
153 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
154 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
155
156 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
157 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
158 TYPE_PNV_CHIP_POWER8E)
159
160 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
161 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
162 TYPE_PNV_CHIP_POWER8)
163
164 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
165 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
166 TYPE_PNV_CHIP_POWER8NVL)
167
168 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
169 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
170 TYPE_PNV_CHIP_POWER9)
171
172 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
173 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
174 TYPE_PNV_CHIP_POWER10)
175
176 /*
177 * This generates a HW chip id depending on an index, as found on a
178 * two socket system with dual chip modules :
179 *
180 * 0x0, 0x1, 0x10, 0x11
181 *
182 * 4 chips should be the maximum
183 *
184 * TODO: use a machine property to define the chip ids
185 */
186 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
187
188 /*
189 * Converts back a HW chip id to an index. This is useful to calculate
190 * the MMIO addresses of some controllers which depend on the chip id.
191 */
192 #define PNV_CHIP_INDEX(chip) \
193 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
194
195 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
196
197 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
198 typedef struct PnvMachineClass PnvMachineClass;
199 typedef struct PnvMachineState PnvMachineState;
200 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
201 PNV_MACHINE, TYPE_PNV_MACHINE)
202
203
204 struct PnvMachineClass {
205 /*< private >*/
206 MachineClass parent_class;
207
208 /*< public >*/
209 const char *compat;
210 int compat_size;
211
212 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
213 };
214
215 struct PnvMachineState {
216 /*< private >*/
217 MachineState parent_obj;
218
219 uint32_t initrd_base;
220 long initrd_size;
221
222 uint32_t num_chips;
223 PnvChip **chips;
224
225 ISABus *isa_bus;
226 uint32_t cpld_irqstate;
227
228 IPMIBmc *bmc;
229 Notifier powerdown_notifier;
230
231 PnvPnor *pnor;
232
233 hwaddr fw_load_addr;
234 };
235
236 #define PNV_FDT_ADDR 0x01000000
237 #define PNV_TIMEBASE_FREQ 512000000ULL
238
239 /*
240 * BMC helpers
241 */
242 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
243 void pnv_bmc_powerdown(IPMIBmc *bmc);
244 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
245 IPMIBmc *pnv_bmc_find(Error **errp);
246 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
247
248 /*
249 * POWER8 MMIO base addresses
250 */
251 #define PNV_XSCOM_SIZE 0x800000000ull
252 #define PNV_XSCOM_BASE(chip) \
253 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
254
255 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
256 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
257 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
258 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
259
260 #define PNV_HOMER_SIZE 0x0000000000400000ull
261 #define PNV_HOMER_BASE(chip) \
262 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
263
264
265 /*
266 * XSCOM 0x20109CA defines the ICP BAR:
267 *
268 * 0:29 : bits 14 to 43 of address to define 1 MB region.
269 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
270 * 31:63 : Constant 0
271 *
272 * Usually defined as :
273 *
274 * 0xffffe00200000000 -> 0x0003ffff80000000
275 * 0xffffe00600000000 -> 0x0003ffff80100000
276 * 0xffffe02200000000 -> 0x0003ffff80800000
277 * 0xffffe02600000000 -> 0x0003ffff80900000
278 */
279 #define PNV_ICP_SIZE 0x0000000000100000ull
280 #define PNV_ICP_BASE(chip) \
281 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
282
283
284 #define PNV_PSIHB_SIZE 0x0000000000100000ull
285 #define PNV_PSIHB_BASE(chip) \
286 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
287
288 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
289 #define PNV_PSIHB_FSP_BASE(chip) \
290 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
291 PNV_PSIHB_FSP_SIZE)
292
293 /*
294 * POWER9 MMIO base addresses
295 */
296 #define PNV9_CHIP_BASE(chip, base) \
297 ((base) + ((uint64_t) (chip)->chip_id << 42))
298
299 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
300 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
301
302 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
303 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
304
305 #define PNV9_LPCM_SIZE 0x0000000100000000ull
306 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
307
308 #define PNV9_PSIHB_SIZE 0x0000000000100000ull
309 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
310
311 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
312 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
313
314 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
315 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
316
317 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
318 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
319
320 #define PNV9_XSCOM_SIZE 0x0000000400000000ull
321 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
322
323 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
324 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
325 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
326 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
327
328 #define PNV9_HOMER_SIZE 0x0000000000400000ull
329 #define PNV9_HOMER_BASE(chip) \
330 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
331
332 /*
333 * POWER10 MMIO base addresses - 16TB stride per chip
334 */
335 #define PNV10_CHIP_BASE(chip, base) \
336 ((base) + ((uint64_t) (chip)->chip_id << 44))
337
338 #define PNV10_XSCOM_SIZE 0x0000000400000000ull
339 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
340
341 #define PNV10_LPCM_SIZE 0x0000000100000000ull
342 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
343
344 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
345 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
346
347 #define PNV10_PSIHB_SIZE 0x0000000000100000ull
348 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
349
350 #endif /* PPC_PNV_H */