Merge tag 'kraxel-20220704-pull-request' of https://gitlab.com/kraxel/qemu into staging
[qemu.git] / include / hw / ppc / pnv.h
1 /*
2 * QEMU PowerPC PowerNV various definitions
3 *
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_PNV_H
21 #define PPC_PNV_H
22
23 #include "hw/boards.h"
24 #include "hw/sysbus.h"
25 #include "hw/ipmi/ipmi.h"
26 #include "hw/ppc/pnv_lpc.h"
27 #include "hw/ppc/pnv_pnor.h"
28 #include "hw/ppc/pnv_psi.h"
29 #include "hw/ppc/pnv_occ.h"
30 #include "hw/ppc/pnv_homer.h"
31 #include "hw/ppc/pnv_xive.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/pci-host/pnv_phb3.h"
34 #include "hw/pci-host/pnv_phb4.h"
35 #include "qom/object.h"
36
37 #define TYPE_PNV_CHIP "pnv-chip"
38 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
39 PNV_CHIP)
40
41 struct PnvChip {
42 /*< private >*/
43 SysBusDevice parent_obj;
44
45 /*< public >*/
46 uint32_t chip_id;
47 uint64_t ram_start;
48 uint64_t ram_size;
49
50 uint32_t nr_cores;
51 uint32_t nr_threads;
52 uint64_t cores_mask;
53 PnvCore **cores;
54
55 uint32_t num_pecs;
56
57 MemoryRegion xscom_mmio;
58 MemoryRegion xscom;
59 AddressSpace xscom_as;
60
61 MemoryRegion *fw_mr;
62 gchar *dt_isa_nodename;
63 };
64
65 #define TYPE_PNV8_CHIP "pnv8-chip"
66 typedef struct Pnv8Chip Pnv8Chip;
67 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
68 TYPE_PNV8_CHIP)
69
70 struct Pnv8Chip {
71 /*< private >*/
72 PnvChip parent_obj;
73
74 /*< public >*/
75 MemoryRegion icp_mmio;
76
77 PnvLpcController lpc;
78 Pnv8Psi psi;
79 PnvOCC occ;
80 PnvHomer homer;
81
82 #define PNV8_CHIP_PHB3_MAX 4
83 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
84 uint32_t num_phbs;
85
86 XICSFabric *xics;
87 };
88
89 #define TYPE_PNV9_CHIP "pnv9-chip"
90 typedef struct Pnv9Chip Pnv9Chip;
91 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
92 TYPE_PNV9_CHIP)
93
94 struct Pnv9Chip {
95 /*< private >*/
96 PnvChip parent_obj;
97
98 /*< public >*/
99 PnvXive xive;
100 Pnv9Psi psi;
101 PnvLpcController lpc;
102 PnvOCC occ;
103 PnvHomer homer;
104
105 uint32_t nr_quads;
106 PnvQuad *quads;
107
108 #define PNV9_CHIP_MAX_PEC 3
109 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
110 };
111
112 /*
113 * A SMT8 fused core is a pair of SMT4 cores.
114 */
115 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
116 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
117
118 #define TYPE_PNV10_CHIP "pnv10-chip"
119 typedef struct Pnv10Chip Pnv10Chip;
120 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
121 TYPE_PNV10_CHIP)
122
123 struct Pnv10Chip {
124 /*< private >*/
125 PnvChip parent_obj;
126
127 /*< public >*/
128 PnvXive2 xive;
129 Pnv9Psi psi;
130 PnvLpcController lpc;
131 PnvOCC occ;
132 PnvHomer homer;
133
134 uint32_t nr_quads;
135 PnvQuad *quads;
136
137 #define PNV10_CHIP_MAX_PEC 2
138 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
139 };
140
141 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
142 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
143
144 struct PnvChipClass {
145 /*< private >*/
146 SysBusDeviceClass parent_class;
147
148 /*< public >*/
149 uint64_t chip_cfam_id;
150 uint64_t cores_mask;
151 uint32_t num_pecs;
152 uint32_t num_phbs;
153
154 DeviceRealize parent_realize;
155
156 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
157 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
158 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
159 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
160 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
161 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
162 void (*dt_populate)(PnvChip *chip, void *fdt);
163 void (*pic_print_info)(PnvChip *chip, Monitor *mon);
164 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
165 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
166 };
167
168 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
169 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
170
171 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
172 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
173 TYPE_PNV_CHIP_POWER8E)
174
175 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
176 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
177 TYPE_PNV_CHIP_POWER8)
178
179 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
180 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
181 TYPE_PNV_CHIP_POWER8NVL)
182
183 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
184 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
185 TYPE_PNV_CHIP_POWER9)
186
187 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
188 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
189 TYPE_PNV_CHIP_POWER10)
190
191 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
192 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name);
193
194 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
195 typedef struct PnvMachineClass PnvMachineClass;
196 typedef struct PnvMachineState PnvMachineState;
197 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
198 PNV_MACHINE, TYPE_PNV_MACHINE)
199
200
201 struct PnvMachineClass {
202 /*< private >*/
203 MachineClass parent_class;
204
205 /*< public >*/
206 const char *compat;
207 int compat_size;
208
209 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
210 };
211
212 struct PnvMachineState {
213 /*< private >*/
214 MachineState parent_obj;
215
216 uint32_t initrd_base;
217 long initrd_size;
218
219 uint32_t num_chips;
220 PnvChip **chips;
221
222 ISABus *isa_bus;
223 uint32_t cpld_irqstate;
224
225 IPMIBmc *bmc;
226 Notifier powerdown_notifier;
227
228 PnvPnor *pnor;
229
230 hwaddr fw_load_addr;
231 };
232
233 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
234
235 #define PNV_FDT_ADDR 0x01000000
236 #define PNV_TIMEBASE_FREQ 512000000ULL
237
238 /*
239 * BMC helpers
240 */
241 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
242 void pnv_bmc_powerdown(IPMIBmc *bmc);
243 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
244 IPMIBmc *pnv_bmc_find(Error **errp);
245 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
246
247 /*
248 * POWER8 MMIO base addresses
249 */
250 #define PNV_XSCOM_SIZE 0x800000000ull
251 #define PNV_XSCOM_BASE(chip) \
252 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
253
254 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
255 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
256 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
257 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
258
259 #define PNV_HOMER_SIZE 0x0000000000400000ull
260 #define PNV_HOMER_BASE(chip) \
261 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
262
263
264 /*
265 * XSCOM 0x20109CA defines the ICP BAR:
266 *
267 * 0:29 : bits 14 to 43 of address to define 1 MB region.
268 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
269 * 31:63 : Constant 0
270 *
271 * Usually defined as :
272 *
273 * 0xffffe00200000000 -> 0x0003ffff80000000
274 * 0xffffe00600000000 -> 0x0003ffff80100000
275 * 0xffffe02200000000 -> 0x0003ffff80800000
276 * 0xffffe02600000000 -> 0x0003ffff80900000
277 */
278 #define PNV_ICP_SIZE 0x0000000000100000ull
279 #define PNV_ICP_BASE(chip) \
280 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
281
282
283 #define PNV_PSIHB_SIZE 0x0000000000100000ull
284 #define PNV_PSIHB_BASE(chip) \
285 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
286
287 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
288 #define PNV_PSIHB_FSP_BASE(chip) \
289 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
290 PNV_PSIHB_FSP_SIZE)
291
292 /*
293 * POWER9 MMIO base addresses
294 */
295 #define PNV9_CHIP_BASE(chip, base) \
296 ((base) + ((uint64_t) (chip)->chip_id << 42))
297
298 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
299 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
300
301 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
302 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
303
304 #define PNV9_LPCM_SIZE 0x0000000100000000ull
305 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
306
307 #define PNV9_PSIHB_SIZE 0x0000000000100000ull
308 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
309
310 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
311 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
312
313 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
314 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
315
316 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
317 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
318
319 #define PNV9_XSCOM_SIZE 0x0000000400000000ull
320 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
321
322 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
323 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
324 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
325 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
326
327 #define PNV9_HOMER_SIZE 0x0000000000400000ull
328 #define PNV9_HOMER_BASE(chip) \
329 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
330
331 /*
332 * POWER10 MMIO base addresses - 16TB stride per chip
333 */
334 #define PNV10_CHIP_BASE(chip, base) \
335 ((base) + ((uint64_t) (chip)->chip_id << 44))
336
337 #define PNV10_XSCOM_SIZE 0x0000000400000000ull
338 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
339
340 #define PNV10_LPCM_SIZE 0x0000000100000000ull
341 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
342
343 #define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
344 #define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
345
346 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
347 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
348
349 #define PNV10_PSIHB_SIZE 0x0000000000100000ull
350 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
351
352 #define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
353 #define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
354
355 #define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
356 #define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
357
358 #define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
359 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
360
361 #define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
362 #define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
363
364 #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
365 #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
366
367 #define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
368 #define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
369 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
370 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
371
372 #define PNV10_HOMER_SIZE 0x0000000000400000ull
373 #define PNV10_HOMER_BASE(chip) \
374 (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
375
376 #endif /* PPC_PNV_H */