Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210504' into staging
[qemu.git] / include / hw / ppc / pnv.h
1 /*
2 * QEMU PowerPC PowerNV various definitions
3 *
4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_PNV_H
21 #define PPC_PNV_H
22
23 #include "hw/boards.h"
24 #include "hw/sysbus.h"
25 #include "hw/ipmi/ipmi.h"
26 #include "hw/ppc/pnv_lpc.h"
27 #include "hw/ppc/pnv_pnor.h"
28 #include "hw/ppc/pnv_psi.h"
29 #include "hw/ppc/pnv_occ.h"
30 #include "hw/ppc/pnv_homer.h"
31 #include "hw/ppc/pnv_xive.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/pci-host/pnv_phb3.h"
34 #include "hw/pci-host/pnv_phb4.h"
35 #include "qom/object.h"
36
37 #define TYPE_PNV_CHIP "pnv-chip"
38 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
39 PNV_CHIP)
40
41 struct PnvChip {
42 /*< private >*/
43 SysBusDevice parent_obj;
44
45 /*< public >*/
46 uint32_t chip_id;
47 uint64_t ram_start;
48 uint64_t ram_size;
49
50 uint32_t nr_cores;
51 uint32_t nr_threads;
52 uint64_t cores_mask;
53 PnvCore **cores;
54
55 uint32_t num_phbs;
56
57 MemoryRegion xscom_mmio;
58 MemoryRegion xscom;
59 AddressSpace xscom_as;
60
61 MemoryRegion *fw_mr;
62 gchar *dt_isa_nodename;
63 };
64
65 #define TYPE_PNV8_CHIP "pnv8-chip"
66 typedef struct Pnv8Chip Pnv8Chip;
67 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
68 TYPE_PNV8_CHIP)
69
70 struct Pnv8Chip {
71 /*< private >*/
72 PnvChip parent_obj;
73
74 /*< public >*/
75 MemoryRegion icp_mmio;
76
77 PnvLpcController lpc;
78 Pnv8Psi psi;
79 PnvOCC occ;
80 PnvHomer homer;
81
82 #define PNV8_CHIP_PHB3_MAX 4
83 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
84
85 XICSFabric *xics;
86 };
87
88 #define TYPE_PNV9_CHIP "pnv9-chip"
89 typedef struct Pnv9Chip Pnv9Chip;
90 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
91 TYPE_PNV9_CHIP)
92
93 struct Pnv9Chip {
94 /*< private >*/
95 PnvChip parent_obj;
96
97 /*< public >*/
98 PnvXive xive;
99 Pnv9Psi psi;
100 PnvLpcController lpc;
101 PnvOCC occ;
102 PnvHomer homer;
103
104 uint32_t nr_quads;
105 PnvQuad *quads;
106
107 #define PNV9_CHIP_MAX_PEC 3
108 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
109 };
110
111 /*
112 * A SMT8 fused core is a pair of SMT4 cores.
113 */
114 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
115 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
116
117 #define TYPE_PNV10_CHIP "pnv10-chip"
118 typedef struct Pnv10Chip Pnv10Chip;
119 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
120 TYPE_PNV10_CHIP)
121
122 struct Pnv10Chip {
123 /*< private >*/
124 PnvChip parent_obj;
125
126 /*< public >*/
127 Pnv9Psi psi;
128 PnvLpcController lpc;
129 };
130
131 struct PnvChipClass {
132 /*< private >*/
133 SysBusDeviceClass parent_class;
134
135 /*< public >*/
136 uint64_t chip_cfam_id;
137 uint64_t cores_mask;
138 uint32_t num_phbs;
139
140 DeviceRealize parent_realize;
141
142 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
143 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
144 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
145 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
146 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
147 ISABus *(*isa_create)(PnvChip *chip, Error **errp);
148 void (*dt_populate)(PnvChip *chip, void *fdt);
149 void (*pic_print_info)(PnvChip *chip, Monitor *mon);
150 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
151 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
152 };
153
154 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
155 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
156
157 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
158 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
159 TYPE_PNV_CHIP_POWER8E)
160
161 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
162 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
163 TYPE_PNV_CHIP_POWER8)
164
165 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
166 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
167 TYPE_PNV_CHIP_POWER8NVL)
168
169 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
170 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
171 TYPE_PNV_CHIP_POWER9)
172
173 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v1.0")
174 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
175 TYPE_PNV_CHIP_POWER10)
176
177 /*
178 * This generates a HW chip id depending on an index, as found on a
179 * two socket system with dual chip modules :
180 *
181 * 0x0, 0x1, 0x10, 0x11
182 *
183 * 4 chips should be the maximum
184 *
185 * TODO: use a machine property to define the chip ids
186 */
187 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
188
189 /*
190 * Converts back a HW chip id to an index. This is useful to calculate
191 * the MMIO addresses of some controllers which depend on the chip id.
192 */
193 #define PNV_CHIP_INDEX(chip) \
194 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
195
196 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
197
198 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
199 typedef struct PnvMachineClass PnvMachineClass;
200 typedef struct PnvMachineState PnvMachineState;
201 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
202 PNV_MACHINE, TYPE_PNV_MACHINE)
203
204
205 struct PnvMachineClass {
206 /*< private >*/
207 MachineClass parent_class;
208
209 /*< public >*/
210 const char *compat;
211 int compat_size;
212
213 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
214 };
215
216 struct PnvMachineState {
217 /*< private >*/
218 MachineState parent_obj;
219
220 uint32_t initrd_base;
221 long initrd_size;
222
223 uint32_t num_chips;
224 PnvChip **chips;
225
226 ISABus *isa_bus;
227 uint32_t cpld_irqstate;
228
229 IPMIBmc *bmc;
230 Notifier powerdown_notifier;
231
232 PnvPnor *pnor;
233
234 hwaddr fw_load_addr;
235 };
236
237 #define PNV_FDT_ADDR 0x01000000
238 #define PNV_TIMEBASE_FREQ 512000000ULL
239
240 /*
241 * BMC helpers
242 */
243 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
244 void pnv_bmc_powerdown(IPMIBmc *bmc);
245 IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
246 IPMIBmc *pnv_bmc_find(Error **errp);
247 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
248
249 /*
250 * POWER8 MMIO base addresses
251 */
252 #define PNV_XSCOM_SIZE 0x800000000ull
253 #define PNV_XSCOM_BASE(chip) \
254 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
255
256 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
257 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
258 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
259 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
260
261 #define PNV_HOMER_SIZE 0x0000000000400000ull
262 #define PNV_HOMER_BASE(chip) \
263 (0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
264
265
266 /*
267 * XSCOM 0x20109CA defines the ICP BAR:
268 *
269 * 0:29 : bits 14 to 43 of address to define 1 MB region.
270 * 30 : 1 to enable ICP to receive loads/stores against its BAR region
271 * 31:63 : Constant 0
272 *
273 * Usually defined as :
274 *
275 * 0xffffe00200000000 -> 0x0003ffff80000000
276 * 0xffffe00600000000 -> 0x0003ffff80100000
277 * 0xffffe02200000000 -> 0x0003ffff80800000
278 * 0xffffe02600000000 -> 0x0003ffff80900000
279 */
280 #define PNV_ICP_SIZE 0x0000000000100000ull
281 #define PNV_ICP_BASE(chip) \
282 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
283
284
285 #define PNV_PSIHB_SIZE 0x0000000000100000ull
286 #define PNV_PSIHB_BASE(chip) \
287 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
288
289 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
290 #define PNV_PSIHB_FSP_BASE(chip) \
291 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
292 PNV_PSIHB_FSP_SIZE)
293
294 /*
295 * POWER9 MMIO base addresses
296 */
297 #define PNV9_CHIP_BASE(chip, base) \
298 ((base) + ((uint64_t) (chip)->chip_id << 42))
299
300 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
301 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
302
303 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
304 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
305
306 #define PNV9_LPCM_SIZE 0x0000000100000000ull
307 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
308
309 #define PNV9_PSIHB_SIZE 0x0000000000100000ull
310 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
311
312 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
313 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
314
315 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
316 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
317
318 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
319 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
320
321 #define PNV9_XSCOM_SIZE 0x0000000400000000ull
322 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
323
324 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
325 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
326 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
327 PNV_OCC_SENSOR_DATA_BLOCK_BASE(PNV_CHIP_INDEX(chip)))
328
329 #define PNV9_HOMER_SIZE 0x0000000000400000ull
330 #define PNV9_HOMER_BASE(chip) \
331 (0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
332
333 /*
334 * POWER10 MMIO base addresses - 16TB stride per chip
335 */
336 #define PNV10_CHIP_BASE(chip, base) \
337 ((base) + ((uint64_t) (chip)->chip_id << 44))
338
339 #define PNV10_XSCOM_SIZE 0x0000000400000000ull
340 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
341
342 #define PNV10_LPCM_SIZE 0x0000000100000000ull
343 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
344
345 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
346 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
347
348 #define PNV10_PSIHB_SIZE 0x0000000000100000ull
349 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
350
351 #endif /* PPC_PNV_H */