pnv/psi: Correct the pnv-psi* devices not to be sysbus devices
[qemu.git] / include / hw / ppc / pnv_psi.h
1 /*
2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
3 *
4 * Copyright (c) 2015-2017, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_PNV_PSI_H
21 #define PPC_PNV_PSI_H
22
23 #include "hw/sysbus.h"
24 #include "hw/ppc/xics.h"
25 #include "hw/ppc/xive.h"
26
27 #define TYPE_PNV_PSI "pnv-psi"
28 #define PNV_PSI(obj) \
29 OBJECT_CHECK(PnvPsi, (obj), TYPE_PNV_PSI)
30
31 #define PSIHB_XSCOM_MAX 0x20
32
33 typedef struct PnvPsi {
34 DeviceState parent;
35
36 MemoryRegion regs_mr;
37 uint64_t bar;
38
39 /* FSP region not supported */
40 /* MemoryRegion fsp_mr; */
41 uint64_t fsp_bar;
42
43 /* Interrupt generation */
44 qemu_irq *qirqs;
45
46 /* Registers */
47 uint64_t regs[PSIHB_XSCOM_MAX];
48
49 MemoryRegion xscom_regs;
50 } PnvPsi;
51
52 #define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
53 #define PNV8_PSI(obj) \
54 OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI)
55
56 typedef struct Pnv8Psi {
57 PnvPsi parent;
58
59 ICSState ics;
60 } Pnv8Psi;
61
62 #define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
63 #define PNV9_PSI(obj) \
64 OBJECT_CHECK(Pnv9Psi, (obj), TYPE_PNV9_PSI)
65
66 typedef struct Pnv9Psi {
67 PnvPsi parent;
68
69 XiveSource source;
70 } Pnv9Psi;
71
72 #define TYPE_PNV10_PSI TYPE_PNV_PSI "-POWER10"
73
74 #define PNV_PSI_CLASS(klass) \
75 OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
76 #define PNV_PSI_GET_CLASS(obj) \
77 OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI)
78
79 typedef struct PnvPsiClass {
80 SysBusDeviceClass parent_class;
81
82 uint32_t xscom_pcba;
83 uint32_t xscom_size;
84 uint64_t bar_mask;
85 const char *compat;
86 int compat_size;
87
88 void (*irq_set)(PnvPsi *psi, int, bool state);
89 } PnvPsiClass;
90
91 /* The PSI and FSP interrupts are muxed on the same IRQ number */
92 typedef enum PnvPsiIrq {
93 PSIHB_IRQ_PSI, /* internal use only */
94 PSIHB_IRQ_FSP, /* internal use only */
95 PSIHB_IRQ_OCC,
96 PSIHB_IRQ_FSI,
97 PSIHB_IRQ_LPC_I2C,
98 PSIHB_IRQ_LOCAL_ERR,
99 PSIHB_IRQ_EXTERNAL,
100 } PnvPsiIrq;
101
102 #define PSI_NUM_INTERRUPTS 6
103
104 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
105
106 /* P9 PSI Interrupts */
107 #define PSIHB9_IRQ_PSI 0
108 #define PSIHB9_IRQ_OCC 1
109 #define PSIHB9_IRQ_FSI 2
110 #define PSIHB9_IRQ_LPCHC 3
111 #define PSIHB9_IRQ_LOCAL_ERR 4
112 #define PSIHB9_IRQ_GLOBAL_ERR 5
113 #define PSIHB9_IRQ_TPM 6
114 #define PSIHB9_IRQ_LPC_SIRQ0 7
115 #define PSIHB9_IRQ_LPC_SIRQ1 8
116 #define PSIHB9_IRQ_LPC_SIRQ2 9
117 #define PSIHB9_IRQ_LPC_SIRQ3 10
118 #define PSIHB9_IRQ_SBE_I2C 11
119 #define PSIHB9_IRQ_DIO 12
120 #define PSIHB9_IRQ_PSU 13
121 #define PSIHB9_NUM_IRQS 14
122
123 void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
124
125 #endif /* PPC_PNV_PSI_H */