Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging
[qemu.git] / include / hw / ppc / pnv_xive.h
1 /*
2 * QEMU PowerPC XIVE interrupt controller model
3 *
4 * Copyright (c) 2017-2019, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #ifndef PPC_PNV_XIVE_H
11 #define PPC_PNV_XIVE_H
12
13 #include "hw/ppc/xive.h"
14 #include "qom/object.h"
15
16 struct PnvChip;
17
18 #define TYPE_PNV_XIVE "pnv-xive"
19 OBJECT_DECLARE_TYPE(PnvXive, PnvXiveClass,
20 PNV_XIVE)
21
22 #define XIVE_BLOCK_MAX 16
23
24 #define XIVE_TABLE_BLK_MAX 16 /* Block Scope Table (0-15) */
25 #define XIVE_TABLE_MIG_MAX 16 /* Migration Register Table (1-15) */
26 #define XIVE_TABLE_VDT_MAX 16 /* VDT Domain Table (0-15) */
27 #define XIVE_TABLE_EDT_MAX 64 /* EDT Domain Table (0-63) */
28
29 struct PnvXive {
30 XiveRouter parent_obj;
31
32 /* Owning chip */
33 struct PnvChip *chip;
34
35 /* XSCOM addresses giving access to the controller registers */
36 MemoryRegion xscom_regs;
37
38 /* Main MMIO regions that can be configured by FW */
39 MemoryRegion ic_mmio;
40 MemoryRegion ic_reg_mmio;
41 MemoryRegion ic_notify_mmio;
42 MemoryRegion ic_lsi_mmio;
43 MemoryRegion tm_indirect_mmio;
44 MemoryRegion vc_mmio;
45 MemoryRegion pc_mmio;
46 MemoryRegion tm_mmio;
47
48 /*
49 * IPI and END address spaces modeling the EDT segmentation in the
50 * VC region
51 */
52 AddressSpace ipi_as;
53 MemoryRegion ipi_mmio;
54 MemoryRegion ipi_edt_mmio;
55
56 AddressSpace end_as;
57 MemoryRegion end_mmio;
58 MemoryRegion end_edt_mmio;
59
60 /* Shortcut values for the Main MMIO regions */
61 hwaddr ic_base;
62 uint32_t ic_shift;
63 hwaddr vc_base;
64 uint32_t vc_shift;
65 hwaddr pc_base;
66 uint32_t pc_shift;
67 hwaddr tm_base;
68 uint32_t tm_shift;
69
70 /* Our XIVE source objects for IPIs and ENDs */
71 XiveSource ipi_source;
72 XiveENDSource end_source;
73
74 /* Interrupt controller registers */
75 uint64_t regs[0x300];
76
77 /*
78 * Virtual Structure Descriptor tables : EAT, SBE, ENDT, NVTT, IRQ
79 * These are in a SRAM protected by ECC.
80 */
81 uint64_t vsds[5][XIVE_BLOCK_MAX];
82
83 /* Translation tables */
84 uint64_t blk[XIVE_TABLE_BLK_MAX];
85 uint64_t mig[XIVE_TABLE_MIG_MAX];
86 uint64_t vdt[XIVE_TABLE_VDT_MAX];
87 uint64_t edt[XIVE_TABLE_EDT_MAX];
88 };
89
90 struct PnvXiveClass {
91 XiveRouterClass parent_class;
92
93 DeviceRealize parent_realize;
94 };
95
96 void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
97
98 #endif /* PPC_PNV_XIVE_H */