Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' into staging
[qemu.git] / include / hw / ppc / ppc.h
1 #ifndef HW_PPC_H
2 #define HW_PPC_H
3
4 #include "target/ppc/cpu-qom.h"
5
6 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
7 PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
8 int ppc_cpu_pir(PowerPCCPU *cpu);
9
10 /* PowerPC hardware exceptions management helpers */
11 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
12 typedef struct clk_setup_t clk_setup_t;
13 struct clk_setup_t {
14 clk_setup_cb cb;
15 void *opaque;
16 };
17 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
18 {
19 if (clk->cb != NULL)
20 (*clk->cb)(clk->opaque, freq);
21 }
22
23 struct ppc_tb_t {
24 /* Time base management */
25 int64_t tb_offset; /* Compensation */
26 int64_t atb_offset; /* Compensation */
27 int64_t vtb_offset;
28 uint32_t tb_freq; /* TB frequency */
29 /* Decrementer management */
30 uint64_t decr_next; /* Tick for next decr interrupt */
31 uint32_t decr_freq; /* decrementer frequency */
32 QEMUTimer *decr_timer;
33 /* Hypervisor decrementer management */
34 uint64_t hdecr_next; /* Tick for next hdecr interrupt */
35 QEMUTimer *hdecr_timer;
36 int64_t purr_offset;
37 void *opaque;
38 uint32_t flags;
39 };
40
41 /* PPC Timers flags */
42 #define PPC_TIMER_BOOKE (1 << 0) /* Enable Booke support */
43 #define PPC_TIMER_E500 (1 << 1) /* Enable e500 support */
44 #define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
45 * the most significant bit
46 * changes from 0 to 1.
47 */
48 #define PPC_DECR_ZERO_TRIGGERED (1 << 3) /* Decr interrupt triggered when
49 * the decrementer reaches zero.
50 */
51 #define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when
52 * the most significant bit is 1.
53 */
54
55 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
56 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
57 /* Embedded PowerPC DCR management */
58 typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
59 typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
60 int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
61 int (*dcr_write_error)(int dcrn));
62 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
63 dcr_read_cb drc_read, dcr_write_cb dcr_write);
64 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
65 unsigned int decr_excp);
66
67 /* Embedded PowerPC reset */
68 void ppc40x_core_reset(PowerPCCPU *cpu);
69 void ppc40x_chip_reset(PowerPCCPU *cpu);
70 void ppc40x_system_reset(PowerPCCPU *cpu);
71
72 #if defined(CONFIG_USER_ONLY)
73 static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
74 static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
75 static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
76 static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
77 static inline void ppcPOWER9_irq_init(PowerPCCPU *cpu) {}
78 static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
79 static inline void ppc_irq_reset(PowerPCCPU *cpu) {}
80 #else
81 void ppc40x_irq_init(PowerPCCPU *cpu);
82 void ppce500_irq_init(PowerPCCPU *cpu);
83 void ppc6xx_irq_init(PowerPCCPU *cpu);
84 void ppc970_irq_init(PowerPCCPU *cpu);
85 void ppcPOWER7_irq_init(PowerPCCPU *cpu);
86 void ppcPOWER9_irq_init(PowerPCCPU *cpu);
87 void ppc_irq_reset(PowerPCCPU *cpu);
88 #endif
89
90 /* PPC machines for OpenBIOS */
91 enum {
92 ARCH_PREP = 0,
93 ARCH_MAC99,
94 ARCH_HEATHROW,
95 ARCH_MAC99_U3,
96 };
97
98 #define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
99 #define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
100 #define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
101 #define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03)
102 #define FW_CFG_PPC_CLOCKFREQ (FW_CFG_ARCH_LOCAL + 0x04)
103 #define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05)
104 #define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06)
105 #define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07)
106 #define FW_CFG_PPC_NVRAM_ADDR (FW_CFG_ARCH_LOCAL + 0x08)
107 #define FW_CFG_PPC_BUSFREQ (FW_CFG_ARCH_LOCAL + 0x09)
108 #define FW_CFG_PPC_NVRAM_FLAT (FW_CFG_ARCH_LOCAL + 0x0a)
109 #define FW_CFG_PPC_VIACONFIG (FW_CFG_ARCH_LOCAL + 0x0b)
110
111 #define PPC_SERIAL_MM_BAUDBASE 399193
112
113 /* ppc_booke.c */
114 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
115 #endif