block/export: Add query-block-exports
[qemu.git] / include / hw / ppc / spapr.h
1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3
4 #include "qemu/units.h"
5 #include "sysemu/dma.h"
6 #include "hw/boards.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 #include "hw/ppc/spapr_irq.h"
11 #include "qom/object.h"
12 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */
13 #include "hw/ppc/xics.h" /* For ICSState */
14 #include "hw/ppc/spapr_tpm_proxy.h"
15
16 struct SpaprVioBus;
17 struct SpaprPhbState;
18 struct SpaprNvram;
19
20 typedef struct SpaprEventLogEntry SpaprEventLogEntry;
21 typedef struct SpaprEventSource SpaprEventSource;
22 typedef struct SpaprPendingHpt SpaprPendingHpt;
23
24 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
25 #define SPAPR_ENTRY_POINT 0x100
26
27 #define SPAPR_TIMEBASE_FREQ 512000000ULL
28
29 #define TYPE_SPAPR_RTC "spapr-rtc"
30
31 OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC)
32
33 struct SpaprRtcState {
34 /*< private >*/
35 DeviceState parent_obj;
36 int64_t ns_offset;
37 };
38
39 typedef struct SpaprDimmState SpaprDimmState;
40
41 #define TYPE_SPAPR_MACHINE "spapr-machine"
42 OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE)
43
44 typedef enum {
45 SPAPR_RESIZE_HPT_DEFAULT = 0,
46 SPAPR_RESIZE_HPT_DISABLED,
47 SPAPR_RESIZE_HPT_ENABLED,
48 SPAPR_RESIZE_HPT_REQUIRED,
49 } SpaprResizeHpt;
50
51 /**
52 * Capabilities
53 */
54
55 /* Hardware Transactional Memory */
56 #define SPAPR_CAP_HTM 0x00
57 /* Vector Scalar Extensions */
58 #define SPAPR_CAP_VSX 0x01
59 /* Decimal Floating Point */
60 #define SPAPR_CAP_DFP 0x02
61 /* Cache Flush on Privilege Change */
62 #define SPAPR_CAP_CFPC 0x03
63 /* Speculation Barrier Bounds Checking */
64 #define SPAPR_CAP_SBBC 0x04
65 /* Indirect Branch Serialisation */
66 #define SPAPR_CAP_IBS 0x05
67 /* HPT Maximum Page Size (encoded as a shift) */
68 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
69 /* Nested KVM-HV */
70 #define SPAPR_CAP_NESTED_KVM_HV 0x07
71 /* Large Decrementer */
72 #define SPAPR_CAP_LARGE_DECREMENTER 0x08
73 /* Count Cache Flush Assist HW Instruction */
74 #define SPAPR_CAP_CCF_ASSIST 0x09
75 /* Implements PAPR FWNMI option */
76 #define SPAPR_CAP_FWNMI 0x0A
77 /* Num Caps */
78 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1)
79
80 /*
81 * Capability Values
82 */
83 /* Bool Caps */
84 #define SPAPR_CAP_OFF 0x00
85 #define SPAPR_CAP_ON 0x01
86
87 /* Custom Caps */
88
89 /* Generic */
90 #define SPAPR_CAP_BROKEN 0x00
91 #define SPAPR_CAP_WORKAROUND 0x01
92 #define SPAPR_CAP_FIXED 0x02
93 /* SPAPR_CAP_IBS (cap-ibs) */
94 #define SPAPR_CAP_FIXED_IBS 0x02
95 #define SPAPR_CAP_FIXED_CCD 0x03
96 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
97
98 #define FDT_MAX_SIZE 0x100000
99
100 /*
101 * NUMA related macros. MAX_DISTANCE_REF_POINTS was taken
102 * from Linux kernel arch/powerpc/mm/numa.h. It represents the
103 * amount of associativity domains for non-CPU resources.
104 *
105 * NUMA_ASSOC_SIZE is the base array size of an ibm,associativity
106 * array for any non-CPU resource.
107 *
108 * VCPU_ASSOC_SIZE represents the size of ibm,associativity array
109 * for CPUs, which has an extra element (vcpu_id) in the end.
110 */
111 #define MAX_DISTANCE_REF_POINTS 4
112 #define NUMA_ASSOC_SIZE (MAX_DISTANCE_REF_POINTS + 1)
113 #define VCPU_ASSOC_SIZE (NUMA_ASSOC_SIZE + 1)
114
115 typedef struct SpaprCapabilities SpaprCapabilities;
116 struct SpaprCapabilities {
117 uint8_t caps[SPAPR_CAP_NUM];
118 };
119
120 /**
121 * SpaprMachineClass:
122 */
123 struct SpaprMachineClass {
124 /*< private >*/
125 MachineClass parent_class;
126
127 /*< public >*/
128 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
129 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */
130 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */
131 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
132 bool pre_2_10_has_unused_icps;
133 bool legacy_irq_allocation;
134 uint32_t nr_xirqs;
135 bool broken_host_serial_model; /* present real host info to the guest */
136 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
137 bool linux_pci_probe;
138 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
139 hwaddr rma_limit; /* clamp the RMA to this size */
140 bool pre_5_1_assoc_refpoints;
141
142 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
143 uint64_t *buid, hwaddr *pio,
144 hwaddr *mmio32, hwaddr *mmio64,
145 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
146 hwaddr *nv2atsd, Error **errp);
147 SpaprResizeHpt resize_hpt_default;
148 SpaprCapabilities default_caps;
149 SpaprIrq *irq;
150 };
151
152 /**
153 * SpaprMachineState:
154 */
155 struct SpaprMachineState {
156 /*< private >*/
157 MachineState parent_obj;
158
159 struct SpaprVioBus *vio_bus;
160 QLIST_HEAD(, SpaprPhbState) phbs;
161 struct SpaprNvram *nvram;
162 SpaprRtcState rtc;
163
164 SpaprResizeHpt resize_hpt;
165 void *htab;
166 uint32_t htab_shift;
167 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
168 SpaprPendingHpt *pending_hpt; /* in-progress resize */
169
170 hwaddr rma_size;
171 uint32_t fdt_size;
172 uint32_t fdt_initial_size;
173 void *fdt_blob;
174 long kernel_size;
175 bool kernel_le;
176 uint64_t kernel_addr;
177 uint32_t initrd_base;
178 long initrd_size;
179 uint64_t rtc_offset; /* Now used only during incoming migration */
180 struct PPCTimebase tb;
181 bool has_graphics;
182 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
183
184 Notifier epow_notifier;
185 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
186 bool use_hotplug_event_source;
187 SpaprEventSource *event_sources;
188
189 /* ibm,client-architecture-support option negotiation */
190 bool cas_pre_isa3_guest;
191 SpaprOptionVector *ov5; /* QEMU-supported option vectors */
192 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
193 uint32_t max_compat_pvr;
194
195 /* Migration state */
196 int htab_save_index;
197 bool htab_first_pass;
198 int htab_fd;
199
200 /* Pending DIMM unplug cache. It is populated when a LMB
201 * unplug starts. It can be regenerated if a migration
202 * occurs during the unplug process. */
203 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
204
205 /* State related to FWNMI option */
206
207 /* System Reset and Machine Check Notification Routine addresses
208 * registered by "ibm,nmi-register" RTAS call.
209 */
210 target_ulong fwnmi_system_reset_addr;
211 target_ulong fwnmi_machine_check_addr;
212
213 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
214 * set to -1 if a FWNMI machine check is not in progress, else is set to
215 * the CPU that was delivered the machine check, and is set back to -1
216 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
217 * to synchronize other CPUs.
218 */
219 int fwnmi_machine_check_interlock;
220 QemuCond fwnmi_machine_check_interlock_cond;
221
222 /*< public >*/
223 char *kvm_type;
224 char *host_model;
225 char *host_serial;
226
227 int32_t irq_map_nr;
228 unsigned long *irq_map;
229 SpaprIrq *irq;
230 qemu_irq *qirqs;
231 SpaprInterruptController *active_intc;
232 ICSState *ics;
233 SpaprXive *xive;
234
235 bool cmd_line_caps[SPAPR_CAP_NUM];
236 SpaprCapabilities def, eff, mig;
237
238 unsigned gpu_numa_id;
239 SpaprTpmProxy *tpm_proxy;
240
241 uint32_t numa_assoc_array[MAX_NODES][NUMA_ASSOC_SIZE];
242
243 Error *fwnmi_migration_blocker;
244 };
245
246 #define H_SUCCESS 0
247 #define H_BUSY 1 /* Hardware busy -- retry later */
248 #define H_CLOSED 2 /* Resource closed */
249 #define H_NOT_AVAILABLE 3
250 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
251 #define H_PARTIAL 5
252 #define H_IN_PROGRESS 14 /* Kind of like busy */
253 #define H_PAGE_REGISTERED 15
254 #define H_PARTIAL_STORE 16
255 #define H_PENDING 17 /* returned from H_POLL_PENDING */
256 #define H_CONTINUE 18 /* Returned from H_Join on success */
257 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
258 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
259 is a good time to retry */
260 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
261 is a good time to retry */
262 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
263 is a good time to retry */
264 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
265 is a good time to retry */
266 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
267 is a good time to retry */
268 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
269 is a good time to retry */
270 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
271 #define H_HARDWARE -1 /* Hardware error */
272 #define H_FUNCTION -2 /* Function not supported */
273 #define H_PRIVILEGE -3 /* Caller not privileged */
274 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
275 #define H_BAD_MODE -5 /* Illegal msr value */
276 #define H_PTEG_FULL -6 /* PTEG is full */
277 #define H_NOT_FOUND -7 /* PTE was not found" */
278 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
279 #define H_NO_MEM -9
280 #define H_AUTHORITY -10
281 #define H_PERMISSION -11
282 #define H_DROPPED -12
283 #define H_SOURCE_PARM -13
284 #define H_DEST_PARM -14
285 #define H_REMOTE_PARM -15
286 #define H_RESOURCE -16
287 #define H_ADAPTER_PARM -17
288 #define H_RH_PARM -18
289 #define H_RCQ_PARM -19
290 #define H_SCQ_PARM -20
291 #define H_EQ_PARM -21
292 #define H_RT_PARM -22
293 #define H_ST_PARM -23
294 #define H_SIGT_PARM -24
295 #define H_TOKEN_PARM -25
296 #define H_MLENGTH_PARM -27
297 #define H_MEM_PARM -28
298 #define H_MEM_ACCESS_PARM -29
299 #define H_ATTR_PARM -30
300 #define H_PORT_PARM -31
301 #define H_MCG_PARM -32
302 #define H_VL_PARM -33
303 #define H_TSIZE_PARM -34
304 #define H_TRACE_PARM -35
305
306 #define H_MASK_PARM -37
307 #define H_MCG_FULL -38
308 #define H_ALIAS_EXIST -39
309 #define H_P_COUNTER -40
310 #define H_TABLE_FULL -41
311 #define H_ALT_TABLE -42
312 #define H_MR_CONDITION -43
313 #define H_NOT_ENOUGH_RESOURCES -44
314 #define H_R_STATE -45
315 #define H_RESCINDEND -46
316 #define H_P2 -55
317 #define H_P3 -56
318 #define H_P4 -57
319 #define H_P5 -58
320 #define H_P6 -59
321 #define H_P7 -60
322 #define H_P8 -61
323 #define H_P9 -62
324 #define H_OVERLAP -68
325 #define H_UNSUPPORTED_FLAG -256
326 #define H_MULTI_THREADS_ACTIVE -9005
327
328
329 /* Long Busy is a condition that can be returned by the firmware
330 * when a call cannot be completed now, but the identical call
331 * should be retried later. This prevents calls blocking in the
332 * firmware for long periods of time. Annoyingly the firmware can return
333 * a range of return codes, hinting at how long we should wait before
334 * retrying. If you don't care for the hint, the macro below is a good
335 * way to check for the long_busy return codes
336 */
337 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
338 && (x <= H_LONG_BUSY_END_RANGE))
339
340 /* Flags */
341 #define H_LARGE_PAGE (1ULL<<(63-16))
342 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
343 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
344 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
345 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
346 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
347 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
348 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
349 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
350 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
351 #define H_ANDCOND (1ULL<<(63-33))
352 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
353 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
354 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
355 #define H_COPY_PAGE (1ULL<<(63-49))
356 #define H_N (1ULL<<(63-61))
357 #define H_PP1 (1ULL<<(63-62))
358 #define H_PP2 (1ULL<<(63-63))
359
360 /* Values for 2nd argument to H_SET_MODE */
361 #define H_SET_MODE_RESOURCE_SET_CIABR 1
362 #define H_SET_MODE_RESOURCE_SET_DAWR 2
363 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
364 #define H_SET_MODE_RESOURCE_LE 4
365
366 /* Flags for H_SET_MODE_RESOURCE_LE */
367 #define H_SET_MODE_ENDIAN_BIG 0
368 #define H_SET_MODE_ENDIAN_LITTLE 1
369
370 /* VASI States */
371 #define H_VASI_INVALID 0
372 #define H_VASI_ENABLED 1
373 #define H_VASI_ABORTED 2
374 #define H_VASI_SUSPENDING 3
375 #define H_VASI_SUSPENDED 4
376 #define H_VASI_RESUMED 5
377 #define H_VASI_COMPLETED 6
378
379 /* DABRX flags */
380 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
381 #define H_DABRX_KERNEL (1ULL<<(63-62))
382 #define H_DABRX_USER (1ULL<<(63-63))
383
384 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
385 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
386 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
387 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
388 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
389 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
390 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
391 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
392 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
393 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
394 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
395 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
396 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
397 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
398
399 /* Each control block has to be on a 4K boundary */
400 #define H_CB_ALIGNMENT 4096
401
402 /* pSeries hypervisor opcodes */
403 #define H_REMOVE 0x04
404 #define H_ENTER 0x08
405 #define H_READ 0x0c
406 #define H_CLEAR_MOD 0x10
407 #define H_CLEAR_REF 0x14
408 #define H_PROTECT 0x18
409 #define H_GET_TCE 0x1c
410 #define H_PUT_TCE 0x20
411 #define H_SET_SPRG0 0x24
412 #define H_SET_DABR 0x28
413 #define H_PAGE_INIT 0x2c
414 #define H_SET_ASR 0x30
415 #define H_ASR_ON 0x34
416 #define H_ASR_OFF 0x38
417 #define H_LOGICAL_CI_LOAD 0x3c
418 #define H_LOGICAL_CI_STORE 0x40
419 #define H_LOGICAL_CACHE_LOAD 0x44
420 #define H_LOGICAL_CACHE_STORE 0x48
421 #define H_LOGICAL_ICBI 0x4c
422 #define H_LOGICAL_DCBF 0x50
423 #define H_GET_TERM_CHAR 0x54
424 #define H_PUT_TERM_CHAR 0x58
425 #define H_REAL_TO_LOGICAL 0x5c
426 #define H_HYPERVISOR_DATA 0x60
427 #define H_EOI 0x64
428 #define H_CPPR 0x68
429 #define H_IPI 0x6c
430 #define H_IPOLL 0x70
431 #define H_XIRR 0x74
432 #define H_PERFMON 0x7c
433 #define H_MIGRATE_DMA 0x78
434 #define H_REGISTER_VPA 0xDC
435 #define H_CEDE 0xE0
436 #define H_CONFER 0xE4
437 #define H_PROD 0xE8
438 #define H_GET_PPP 0xEC
439 #define H_SET_PPP 0xF0
440 #define H_PURR 0xF4
441 #define H_PIC 0xF8
442 #define H_REG_CRQ 0xFC
443 #define H_FREE_CRQ 0x100
444 #define H_VIO_SIGNAL 0x104
445 #define H_SEND_CRQ 0x108
446 #define H_COPY_RDMA 0x110
447 #define H_REGISTER_LOGICAL_LAN 0x114
448 #define H_FREE_LOGICAL_LAN 0x118
449 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
450 #define H_SEND_LOGICAL_LAN 0x120
451 #define H_BULK_REMOVE 0x124
452 #define H_MULTICAST_CTRL 0x130
453 #define H_SET_XDABR 0x134
454 #define H_STUFF_TCE 0x138
455 #define H_PUT_TCE_INDIRECT 0x13C
456 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
457 #define H_VTERM_PARTNER_INFO 0x150
458 #define H_REGISTER_VTERM 0x154
459 #define H_FREE_VTERM 0x158
460 #define H_RESET_EVENTS 0x15C
461 #define H_ALLOC_RESOURCE 0x160
462 #define H_FREE_RESOURCE 0x164
463 #define H_MODIFY_QP 0x168
464 #define H_QUERY_QP 0x16C
465 #define H_REREGISTER_PMR 0x170
466 #define H_REGISTER_SMR 0x174
467 #define H_QUERY_MR 0x178
468 #define H_QUERY_MW 0x17C
469 #define H_QUERY_HCA 0x180
470 #define H_QUERY_PORT 0x184
471 #define H_MODIFY_PORT 0x188
472 #define H_DEFINE_AQP1 0x18C
473 #define H_GET_TRACE_BUFFER 0x190
474 #define H_DEFINE_AQP0 0x194
475 #define H_RESIZE_MR 0x198
476 #define H_ATTACH_MCQP 0x19C
477 #define H_DETACH_MCQP 0x1A0
478 #define H_CREATE_RPT 0x1A4
479 #define H_REMOVE_RPT 0x1A8
480 #define H_REGISTER_RPAGES 0x1AC
481 #define H_DISABLE_AND_GETC 0x1B0
482 #define H_ERROR_DATA 0x1B4
483 #define H_GET_HCA_INFO 0x1B8
484 #define H_GET_PERF_COUNT 0x1BC
485 #define H_MANAGE_TRACE 0x1C0
486 #define H_GET_CPU_CHARACTERISTICS 0x1C8
487 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
488 #define H_QUERY_INT_STATE 0x1E4
489 #define H_POLL_PENDING 0x1D8
490 #define H_ILLAN_ATTRIBUTES 0x244
491 #define H_MODIFY_HEA_QP 0x250
492 #define H_QUERY_HEA_QP 0x254
493 #define H_QUERY_HEA 0x258
494 #define H_QUERY_HEA_PORT 0x25C
495 #define H_MODIFY_HEA_PORT 0x260
496 #define H_REG_BCMC 0x264
497 #define H_DEREG_BCMC 0x268
498 #define H_REGISTER_HEA_RPAGES 0x26C
499 #define H_DISABLE_AND_GET_HEA 0x270
500 #define H_GET_HEA_INFO 0x274
501 #define H_ALLOC_HEA_RESOURCE 0x278
502 #define H_ADD_CONN 0x284
503 #define H_DEL_CONN 0x288
504 #define H_JOIN 0x298
505 #define H_VASI_STATE 0x2A4
506 #define H_ENABLE_CRQ 0x2B0
507 #define H_GET_EM_PARMS 0x2B8
508 #define H_SET_MPP 0x2D0
509 #define H_GET_MPP 0x2D4
510 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
511 #define H_XIRR_X 0x2FC
512 #define H_RANDOM 0x300
513 #define H_SET_MODE 0x31C
514 #define H_RESIZE_HPT_PREPARE 0x36C
515 #define H_RESIZE_HPT_COMMIT 0x370
516 #define H_CLEAN_SLB 0x374
517 #define H_INVALIDATE_PID 0x378
518 #define H_REGISTER_PROC_TBL 0x37C
519 #define H_SIGNAL_SYS_RESET 0x380
520
521 #define H_INT_GET_SOURCE_INFO 0x3A8
522 #define H_INT_SET_SOURCE_CONFIG 0x3AC
523 #define H_INT_GET_SOURCE_CONFIG 0x3B0
524 #define H_INT_GET_QUEUE_INFO 0x3B4
525 #define H_INT_SET_QUEUE_CONFIG 0x3B8
526 #define H_INT_GET_QUEUE_CONFIG 0x3BC
527 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
528 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
529 #define H_INT_ESB 0x3C8
530 #define H_INT_SYNC 0x3CC
531 #define H_INT_RESET 0x3D0
532 #define H_SCM_READ_METADATA 0x3E4
533 #define H_SCM_WRITE_METADATA 0x3E8
534 #define H_SCM_BIND_MEM 0x3EC
535 #define H_SCM_UNBIND_MEM 0x3F0
536 #define H_SCM_UNBIND_ALL 0x3FC
537
538 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL
539
540 /* The hcalls above are standardized in PAPR and implemented by pHyp
541 * as well.
542 *
543 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
544 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
545 * for "platform-specific" hcalls.
546 */
547 #define KVMPPC_HCALL_BASE 0xf000
548 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
549 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
550 /* Client Architecture support */
551 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
552 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
553 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
554
555 /*
556 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
557 * Secure VM mode via an Ultravisor / Protected Execution Facility
558 */
559 #define SVM_HCALL_BASE 0xEF00
560 #define SVM_H_TPM_COMM 0xEF10
561 #define SVM_HCALL_MAX SVM_H_TPM_COMM
562
563
564 typedef struct SpaprDeviceTreeUpdateHeader {
565 uint32_t version_id;
566 } SpaprDeviceTreeUpdateHeader;
567
568 #define hcall_dprintf(fmt, ...) \
569 do { \
570 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
571 } while (0)
572
573 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
574 target_ulong opcode,
575 target_ulong *args);
576
577 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
578 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
579 target_ulong *args);
580
581 target_ulong do_client_architecture_support(PowerPCCPU *cpu,
582 SpaprMachineState *spapr,
583 target_ulong addr,
584 target_ulong fdt_bufsize);
585
586 /* Virtual Processor Area structure constants */
587 #define VPA_MIN_SIZE 640
588 #define VPA_SIZE_OFFSET 0x4
589 #define VPA_SHARED_PROC_OFFSET 0x9
590 #define VPA_SHARED_PROC_VAL 0x2
591 #define VPA_DISPATCH_COUNTER 0x100
592
593 /* ibm,set-eeh-option */
594 #define RTAS_EEH_DISABLE 0
595 #define RTAS_EEH_ENABLE 1
596 #define RTAS_EEH_THAW_IO 2
597 #define RTAS_EEH_THAW_DMA 3
598
599 /* ibm,get-config-addr-info2 */
600 #define RTAS_GET_PE_ADDR 0
601 #define RTAS_GET_PE_MODE 1
602 #define RTAS_PE_MODE_NONE 0
603 #define RTAS_PE_MODE_NOT_SHARED 1
604 #define RTAS_PE_MODE_SHARED 2
605
606 /* ibm,read-slot-reset-state2 */
607 #define RTAS_EEH_PE_STATE_NORMAL 0
608 #define RTAS_EEH_PE_STATE_RESET 1
609 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
610 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
611 #define RTAS_EEH_PE_STATE_UNAVAIL 5
612 #define RTAS_EEH_NOT_SUPPORT 0
613 #define RTAS_EEH_SUPPORT 1
614 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
615 #define RTAS_EEH_PE_RECOVER_INFO 0
616
617 /* ibm,set-slot-reset */
618 #define RTAS_SLOT_RESET_DEACTIVATE 0
619 #define RTAS_SLOT_RESET_HOT 1
620 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
621
622 /* ibm,slot-error-detail */
623 #define RTAS_SLOT_TEMP_ERR_LOG 1
624 #define RTAS_SLOT_PERM_ERR_LOG 2
625
626 /* RTAS return codes */
627 #define RTAS_OUT_SUCCESS 0
628 #define RTAS_OUT_NO_ERRORS_FOUND 1
629 #define RTAS_OUT_HW_ERROR -1
630 #define RTAS_OUT_BUSY -2
631 #define RTAS_OUT_PARAM_ERROR -3
632 #define RTAS_OUT_NOT_SUPPORTED -3
633 #define RTAS_OUT_NO_SUCH_INDICATOR -3
634 #define RTAS_OUT_NOT_AUTHORIZED -9002
635 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
636
637 /* DDW pagesize mask values from ibm,query-pe-dma-window */
638 #define RTAS_DDW_PGSIZE_4K 0x01
639 #define RTAS_DDW_PGSIZE_64K 0x02
640 #define RTAS_DDW_PGSIZE_16M 0x04
641 #define RTAS_DDW_PGSIZE_32M 0x08
642 #define RTAS_DDW_PGSIZE_64M 0x10
643 #define RTAS_DDW_PGSIZE_128M 0x20
644 #define RTAS_DDW_PGSIZE_256M 0x40
645 #define RTAS_DDW_PGSIZE_16G 0x80
646
647 /* RTAS tokens */
648 #define RTAS_TOKEN_BASE 0x2000
649
650 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
651 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
652 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
653 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
654 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
655 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
656 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
657 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
658 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
659 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
660 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
661 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
662 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
663 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
664 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
665 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
666 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
667 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
668 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
669 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
670 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
671 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
672 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
673 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
674 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
675 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
676 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
677 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
678 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
679 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
680 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
681 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
682 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
683 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
684 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
685 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
686 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
687 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
688 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
689 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
690 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
691 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
692 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A)
693 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
694 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
695
696 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D)
697
698 /* RTAS ibm,get-system-parameter token values */
699 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
700 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
701 #define RTAS_SYSPARM_UUID 48
702
703 /* RTAS indicator/sensor types
704 *
705 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
706 *
707 * NOTE: currently only DR-related sensors are implemented here
708 */
709 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
710 #define RTAS_SENSOR_TYPE_DR 9002
711 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
712 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
713
714 /* Possible values for the platform-processor-diagnostics-run-mode parameter
715 * of the RTAS ibm,get-system-parameter call.
716 */
717 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
718 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
719 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
720 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
721
722 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
723 {
724 return addr & ~0xF000000000000000ULL;
725 }
726
727 static inline uint32_t rtas_ld(target_ulong phys, int n)
728 {
729 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
730 }
731
732 static inline uint64_t rtas_ldq(target_ulong phys, int n)
733 {
734 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
735 }
736
737 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
738 {
739 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
740 }
741
742 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
743 uint32_t token,
744 uint32_t nargs, target_ulong args,
745 uint32_t nret, target_ulong rets);
746 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
747 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
748 uint32_t token, uint32_t nargs, target_ulong args,
749 uint32_t nret, target_ulong rets);
750 void spapr_dt_rtas_tokens(void *fdt, int rtas);
751 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
752
753 #define SPAPR_TCE_PAGE_SHIFT 12
754 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
755 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
756
757 #define SPAPR_VIO_BASE_LIOBN 0x00000000
758 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
759 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
760 (0x80000000 | ((phb_index) << 8) | (window_num))
761 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
762 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
763
764 #define RTAS_SIZE 2048
765 #define RTAS_ERROR_LOG_MAX 2048
766
767 /* Offset from rtas-base where error log is placed */
768 #define RTAS_ERROR_LOG_OFFSET 0x30
769
770 #define RTAS_EVENT_SCAN_RATE 1
771
772 /* This helper should be used to encode interrupt specifiers when the related
773 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
774 * VIO devices, RTAS event sources and PHBs).
775 */
776 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
777 {
778 intspec[0] = cpu_to_be32(irq);
779 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
780 }
781
782
783 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
784 OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE)
785
786 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
787 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION,
788 TYPE_SPAPR_IOMMU_MEMORY_REGION)
789
790 struct SpaprTceTable {
791 DeviceState parent;
792 uint32_t liobn;
793 uint32_t nb_table;
794 uint64_t bus_offset;
795 uint32_t page_shift;
796 uint64_t *table;
797 uint32_t mig_nb_table;
798 uint64_t *mig_table;
799 bool bypass;
800 bool need_vfio;
801 bool skipping_replay;
802 int fd;
803 MemoryRegion root;
804 IOMMUMemoryRegion iommu;
805 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
806 QLIST_ENTRY(SpaprTceTable) list;
807 };
808
809 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
810
811 struct SpaprEventLogEntry {
812 uint32_t summary;
813 uint32_t extended_length;
814 void *extended_log;
815 QTAILQ_ENTRY(SpaprEventLogEntry) next;
816 };
817
818 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
819 void spapr_events_init(SpaprMachineState *sm);
820 void spapr_dt_events(SpaprMachineState *sm, void *fdt);
821 void close_htab_fd(SpaprMachineState *spapr);
822 void spapr_setup_hpt(SpaprMachineState *spapr);
823 void spapr_free_hpt(SpaprMachineState *spapr);
824 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
825 void spapr_tce_table_enable(SpaprTceTable *tcet,
826 uint32_t page_shift, uint64_t bus_offset,
827 uint32_t nb_table);
828 void spapr_tce_table_disable(SpaprTceTable *tcet);
829 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
830
831 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
832 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
833 uint32_t liobn, uint64_t window, uint32_t size);
834 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
835 SpaprTceTable *tcet);
836 void spapr_pci_switch_vga(bool big_endian);
837 void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
838 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
839 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
840 uint32_t count);
841 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
842 uint32_t count);
843 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
844 uint32_t count, uint32_t index);
845 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
846 uint32_t count, uint32_t index);
847 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
848 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
849 Error **errp);
850 void spapr_clear_pending_events(SpaprMachineState *spapr);
851 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
852 int spapr_max_server_number(SpaprMachineState *spapr);
853 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
854 uint64_t pte0, uint64_t pte1);
855 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
856
857 /* DRC callbacks. */
858 void spapr_core_release(DeviceState *dev);
859 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
860 void *fdt, int *fdt_start_offset, Error **errp);
861 void spapr_lmb_release(DeviceState *dev);
862 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
863 void *fdt, int *fdt_start_offset, Error **errp);
864 void spapr_phb_release(DeviceState *dev);
865 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
866 void *fdt, int *fdt_start_offset, Error **errp);
867
868 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
869 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
870
871 #define TYPE_SPAPR_RNG "spapr-rng"
872
873 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
874
875 /*
876 * This defines the maximum number of DIMM slots we can have for sPAPR
877 * guest. This is not defined by sPAPR but we are defining it to 32 slots
878 * based on default number of slots provided by PowerPC kernel.
879 */
880 #define SPAPR_MAX_RAM_SLOTS 32
881
882 /* 1GB alignment for hotplug memory region */
883 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
884
885 /*
886 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
887 * property under ibm,dynamic-reconfiguration-memory node.
888 */
889 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
890
891 /*
892 * Defines for flag value in ibm,dynamic-memory property under
893 * ibm,dynamic-reconfiguration-memory node.
894 */
895 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
896 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
897 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
898 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
899
900 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
901
902 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
903
904 int spapr_get_vcpu_id(PowerPCCPU *cpu);
905 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
906 PowerPCCPU *spapr_find_cpu(int vcpu_id);
907
908 int spapr_caps_pre_load(void *opaque);
909 int spapr_caps_pre_save(void *opaque);
910
911 /*
912 * Handling of optional capabilities
913 */
914 extern const VMStateDescription vmstate_spapr_cap_htm;
915 extern const VMStateDescription vmstate_spapr_cap_vsx;
916 extern const VMStateDescription vmstate_spapr_cap_dfp;
917 extern const VMStateDescription vmstate_spapr_cap_cfpc;
918 extern const VMStateDescription vmstate_spapr_cap_sbbc;
919 extern const VMStateDescription vmstate_spapr_cap_ibs;
920 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
921 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
922 extern const VMStateDescription vmstate_spapr_cap_large_decr;
923 extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
924 extern const VMStateDescription vmstate_spapr_cap_fwnmi;
925
926 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
927 {
928 return spapr->eff.caps[cap];
929 }
930
931 void spapr_caps_init(SpaprMachineState *spapr);
932 void spapr_caps_apply(SpaprMachineState *spapr);
933 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
934 void spapr_caps_add_properties(SpaprMachineClass *smc);
935 int spapr_caps_post_migration(SpaprMachineState *spapr);
936
937 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
938 Error **errp);
939 /*
940 * XIVE definitions
941 */
942 #define SPAPR_OV5_XIVE_LEGACY 0x0
943 #define SPAPR_OV5_XIVE_EXPLOIT 0x40
944 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */
945
946 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
947 hwaddr spapr_get_rtas_addr(void);
948 #endif /* HW_SPAPR_H */