hw/clock: Only propagate clock changes if the clock is changed
[qemu.git] / include / hw / ppc / spapr.h
1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3
4 #include "qemu/units.h"
5 #include "sysemu/dma.h"
6 #include "hw/boards.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 #include "hw/ppc/spapr_irq.h"
11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */
12 #include "hw/ppc/xics.h" /* For ICSState */
13 #include "hw/ppc/spapr_tpm_proxy.h"
14
15 struct SpaprVioBus;
16 struct SpaprPhbState;
17 struct SpaprNvram;
18
19 typedef struct SpaprEventLogEntry SpaprEventLogEntry;
20 typedef struct SpaprEventSource SpaprEventSource;
21 typedef struct SpaprPendingHpt SpaprPendingHpt;
22
23 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
24 #define SPAPR_ENTRY_POINT 0x100
25
26 #define SPAPR_TIMEBASE_FREQ 512000000ULL
27
28 #define TYPE_SPAPR_RTC "spapr-rtc"
29
30 #define SPAPR_RTC(obj) \
31 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC)
32
33 typedef struct SpaprRtcState SpaprRtcState;
34 struct SpaprRtcState {
35 /*< private >*/
36 DeviceState parent_obj;
37 int64_t ns_offset;
38 };
39
40 typedef struct SpaprDimmState SpaprDimmState;
41 typedef struct SpaprMachineClass SpaprMachineClass;
42
43 #define TYPE_SPAPR_MACHINE "spapr-machine"
44 #define SPAPR_MACHINE(obj) \
45 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
46 #define SPAPR_MACHINE_GET_CLASS(obj) \
47 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE)
48 #define SPAPR_MACHINE_CLASS(klass) \
49 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE)
50
51 typedef enum {
52 SPAPR_RESIZE_HPT_DEFAULT = 0,
53 SPAPR_RESIZE_HPT_DISABLED,
54 SPAPR_RESIZE_HPT_ENABLED,
55 SPAPR_RESIZE_HPT_REQUIRED,
56 } SpaprResizeHpt;
57
58 /**
59 * Capabilities
60 */
61
62 /* Hardware Transactional Memory */
63 #define SPAPR_CAP_HTM 0x00
64 /* Vector Scalar Extensions */
65 #define SPAPR_CAP_VSX 0x01
66 /* Decimal Floating Point */
67 #define SPAPR_CAP_DFP 0x02
68 /* Cache Flush on Privilege Change */
69 #define SPAPR_CAP_CFPC 0x03
70 /* Speculation Barrier Bounds Checking */
71 #define SPAPR_CAP_SBBC 0x04
72 /* Indirect Branch Serialisation */
73 #define SPAPR_CAP_IBS 0x05
74 /* HPT Maximum Page Size (encoded as a shift) */
75 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
76 /* Nested KVM-HV */
77 #define SPAPR_CAP_NESTED_KVM_HV 0x07
78 /* Large Decrementer */
79 #define SPAPR_CAP_LARGE_DECREMENTER 0x08
80 /* Count Cache Flush Assist HW Instruction */
81 #define SPAPR_CAP_CCF_ASSIST 0x09
82 /* Implements PAPR FWNMI option */
83 #define SPAPR_CAP_FWNMI 0x0A
84 /* Num Caps */
85 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1)
86
87 /*
88 * Capability Values
89 */
90 /* Bool Caps */
91 #define SPAPR_CAP_OFF 0x00
92 #define SPAPR_CAP_ON 0x01
93
94 /* Custom Caps */
95
96 /* Generic */
97 #define SPAPR_CAP_BROKEN 0x00
98 #define SPAPR_CAP_WORKAROUND 0x01
99 #define SPAPR_CAP_FIXED 0x02
100 /* SPAPR_CAP_IBS (cap-ibs) */
101 #define SPAPR_CAP_FIXED_IBS 0x02
102 #define SPAPR_CAP_FIXED_CCD 0x03
103 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
104
105 #define FDT_MAX_SIZE 0x100000
106
107 typedef struct SpaprCapabilities SpaprCapabilities;
108 struct SpaprCapabilities {
109 uint8_t caps[SPAPR_CAP_NUM];
110 };
111
112 /**
113 * SpaprMachineClass:
114 */
115 struct SpaprMachineClass {
116 /*< private >*/
117 MachineClass parent_class;
118
119 /*< public >*/
120 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
121 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */
122 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */
123 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
124 bool pre_2_10_has_unused_icps;
125 bool legacy_irq_allocation;
126 uint32_t nr_xirqs;
127 bool broken_host_serial_model; /* present real host info to the guest */
128 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
129 bool linux_pci_probe;
130 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
131 hwaddr rma_limit; /* clamp the RMA to this size */
132 bool pre_5_1_assoc_refpoints;
133
134 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
135 uint64_t *buid, hwaddr *pio,
136 hwaddr *mmio32, hwaddr *mmio64,
137 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
138 hwaddr *nv2atsd, Error **errp);
139 SpaprResizeHpt resize_hpt_default;
140 SpaprCapabilities default_caps;
141 SpaprIrq *irq;
142 };
143
144 /**
145 * SpaprMachineState:
146 */
147 struct SpaprMachineState {
148 /*< private >*/
149 MachineState parent_obj;
150
151 struct SpaprVioBus *vio_bus;
152 QLIST_HEAD(, SpaprPhbState) phbs;
153 struct SpaprNvram *nvram;
154 SpaprRtcState rtc;
155
156 SpaprResizeHpt resize_hpt;
157 void *htab;
158 uint32_t htab_shift;
159 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
160 SpaprPendingHpt *pending_hpt; /* in-progress resize */
161
162 hwaddr rma_size;
163 uint32_t fdt_size;
164 uint32_t fdt_initial_size;
165 void *fdt_blob;
166 long kernel_size;
167 bool kernel_le;
168 uint64_t kernel_addr;
169 uint32_t initrd_base;
170 long initrd_size;
171 uint64_t rtc_offset; /* Now used only during incoming migration */
172 struct PPCTimebase tb;
173 bool has_graphics;
174 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
175
176 Notifier epow_notifier;
177 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
178 bool use_hotplug_event_source;
179 SpaprEventSource *event_sources;
180
181 /* ibm,client-architecture-support option negotiation */
182 bool cas_pre_isa3_guest;
183 SpaprOptionVector *ov5; /* QEMU-supported option vectors */
184 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
185 uint32_t max_compat_pvr;
186
187 /* Migration state */
188 int htab_save_index;
189 bool htab_first_pass;
190 int htab_fd;
191
192 /* Pending DIMM unplug cache. It is populated when a LMB
193 * unplug starts. It can be regenerated if a migration
194 * occurs during the unplug process. */
195 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
196
197 /* State related to FWNMI option */
198
199 /* System Reset and Machine Check Notification Routine addresses
200 * registered by "ibm,nmi-register" RTAS call.
201 */
202 target_ulong fwnmi_system_reset_addr;
203 target_ulong fwnmi_machine_check_addr;
204
205 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
206 * set to -1 if a FWNMI machine check is not in progress, else is set to
207 * the CPU that was delivered the machine check, and is set back to -1
208 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
209 * to synchronize other CPUs.
210 */
211 int fwnmi_machine_check_interlock;
212 QemuCond fwnmi_machine_check_interlock_cond;
213
214 /*< public >*/
215 char *kvm_type;
216 char *host_model;
217 char *host_serial;
218
219 int32_t irq_map_nr;
220 unsigned long *irq_map;
221 SpaprIrq *irq;
222 qemu_irq *qirqs;
223 SpaprInterruptController *active_intc;
224 ICSState *ics;
225 SpaprXive *xive;
226
227 bool cmd_line_caps[SPAPR_CAP_NUM];
228 SpaprCapabilities def, eff, mig;
229
230 unsigned gpu_numa_id;
231 SpaprTpmProxy *tpm_proxy;
232
233 Error *fwnmi_migration_blocker;
234 };
235
236 #define H_SUCCESS 0
237 #define H_BUSY 1 /* Hardware busy -- retry later */
238 #define H_CLOSED 2 /* Resource closed */
239 #define H_NOT_AVAILABLE 3
240 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
241 #define H_PARTIAL 5
242 #define H_IN_PROGRESS 14 /* Kind of like busy */
243 #define H_PAGE_REGISTERED 15
244 #define H_PARTIAL_STORE 16
245 #define H_PENDING 17 /* returned from H_POLL_PENDING */
246 #define H_CONTINUE 18 /* Returned from H_Join on success */
247 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
248 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
249 is a good time to retry */
250 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
251 is a good time to retry */
252 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
253 is a good time to retry */
254 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
255 is a good time to retry */
256 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
257 is a good time to retry */
258 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
259 is a good time to retry */
260 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
261 #define H_HARDWARE -1 /* Hardware error */
262 #define H_FUNCTION -2 /* Function not supported */
263 #define H_PRIVILEGE -3 /* Caller not privileged */
264 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
265 #define H_BAD_MODE -5 /* Illegal msr value */
266 #define H_PTEG_FULL -6 /* PTEG is full */
267 #define H_NOT_FOUND -7 /* PTE was not found" */
268 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
269 #define H_NO_MEM -9
270 #define H_AUTHORITY -10
271 #define H_PERMISSION -11
272 #define H_DROPPED -12
273 #define H_SOURCE_PARM -13
274 #define H_DEST_PARM -14
275 #define H_REMOTE_PARM -15
276 #define H_RESOURCE -16
277 #define H_ADAPTER_PARM -17
278 #define H_RH_PARM -18
279 #define H_RCQ_PARM -19
280 #define H_SCQ_PARM -20
281 #define H_EQ_PARM -21
282 #define H_RT_PARM -22
283 #define H_ST_PARM -23
284 #define H_SIGT_PARM -24
285 #define H_TOKEN_PARM -25
286 #define H_MLENGTH_PARM -27
287 #define H_MEM_PARM -28
288 #define H_MEM_ACCESS_PARM -29
289 #define H_ATTR_PARM -30
290 #define H_PORT_PARM -31
291 #define H_MCG_PARM -32
292 #define H_VL_PARM -33
293 #define H_TSIZE_PARM -34
294 #define H_TRACE_PARM -35
295
296 #define H_MASK_PARM -37
297 #define H_MCG_FULL -38
298 #define H_ALIAS_EXIST -39
299 #define H_P_COUNTER -40
300 #define H_TABLE_FULL -41
301 #define H_ALT_TABLE -42
302 #define H_MR_CONDITION -43
303 #define H_NOT_ENOUGH_RESOURCES -44
304 #define H_R_STATE -45
305 #define H_RESCINDEND -46
306 #define H_P2 -55
307 #define H_P3 -56
308 #define H_P4 -57
309 #define H_P5 -58
310 #define H_P6 -59
311 #define H_P7 -60
312 #define H_P8 -61
313 #define H_P9 -62
314 #define H_OVERLAP -68
315 #define H_UNSUPPORTED_FLAG -256
316 #define H_MULTI_THREADS_ACTIVE -9005
317
318
319 /* Long Busy is a condition that can be returned by the firmware
320 * when a call cannot be completed now, but the identical call
321 * should be retried later. This prevents calls blocking in the
322 * firmware for long periods of time. Annoyingly the firmware can return
323 * a range of return codes, hinting at how long we should wait before
324 * retrying. If you don't care for the hint, the macro below is a good
325 * way to check for the long_busy return codes
326 */
327 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
328 && (x <= H_LONG_BUSY_END_RANGE))
329
330 /* Flags */
331 #define H_LARGE_PAGE (1ULL<<(63-16))
332 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
333 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
334 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
335 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
336 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
337 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
338 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
339 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
340 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
341 #define H_ANDCOND (1ULL<<(63-33))
342 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
343 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
344 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
345 #define H_COPY_PAGE (1ULL<<(63-49))
346 #define H_N (1ULL<<(63-61))
347 #define H_PP1 (1ULL<<(63-62))
348 #define H_PP2 (1ULL<<(63-63))
349
350 /* Values for 2nd argument to H_SET_MODE */
351 #define H_SET_MODE_RESOURCE_SET_CIABR 1
352 #define H_SET_MODE_RESOURCE_SET_DAWR 2
353 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
354 #define H_SET_MODE_RESOURCE_LE 4
355
356 /* Flags for H_SET_MODE_RESOURCE_LE */
357 #define H_SET_MODE_ENDIAN_BIG 0
358 #define H_SET_MODE_ENDIAN_LITTLE 1
359
360 /* VASI States */
361 #define H_VASI_INVALID 0
362 #define H_VASI_ENABLED 1
363 #define H_VASI_ABORTED 2
364 #define H_VASI_SUSPENDING 3
365 #define H_VASI_SUSPENDED 4
366 #define H_VASI_RESUMED 5
367 #define H_VASI_COMPLETED 6
368
369 /* DABRX flags */
370 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
371 #define H_DABRX_KERNEL (1ULL<<(63-62))
372 #define H_DABRX_USER (1ULL<<(63-63))
373
374 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
375 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
376 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
377 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
378 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
379 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
380 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
381 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
382 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
383 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
384 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
385 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
386 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
387 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
388
389 /* Each control block has to be on a 4K boundary */
390 #define H_CB_ALIGNMENT 4096
391
392 /* pSeries hypervisor opcodes */
393 #define H_REMOVE 0x04
394 #define H_ENTER 0x08
395 #define H_READ 0x0c
396 #define H_CLEAR_MOD 0x10
397 #define H_CLEAR_REF 0x14
398 #define H_PROTECT 0x18
399 #define H_GET_TCE 0x1c
400 #define H_PUT_TCE 0x20
401 #define H_SET_SPRG0 0x24
402 #define H_SET_DABR 0x28
403 #define H_PAGE_INIT 0x2c
404 #define H_SET_ASR 0x30
405 #define H_ASR_ON 0x34
406 #define H_ASR_OFF 0x38
407 #define H_LOGICAL_CI_LOAD 0x3c
408 #define H_LOGICAL_CI_STORE 0x40
409 #define H_LOGICAL_CACHE_LOAD 0x44
410 #define H_LOGICAL_CACHE_STORE 0x48
411 #define H_LOGICAL_ICBI 0x4c
412 #define H_LOGICAL_DCBF 0x50
413 #define H_GET_TERM_CHAR 0x54
414 #define H_PUT_TERM_CHAR 0x58
415 #define H_REAL_TO_LOGICAL 0x5c
416 #define H_HYPERVISOR_DATA 0x60
417 #define H_EOI 0x64
418 #define H_CPPR 0x68
419 #define H_IPI 0x6c
420 #define H_IPOLL 0x70
421 #define H_XIRR 0x74
422 #define H_PERFMON 0x7c
423 #define H_MIGRATE_DMA 0x78
424 #define H_REGISTER_VPA 0xDC
425 #define H_CEDE 0xE0
426 #define H_CONFER 0xE4
427 #define H_PROD 0xE8
428 #define H_GET_PPP 0xEC
429 #define H_SET_PPP 0xF0
430 #define H_PURR 0xF4
431 #define H_PIC 0xF8
432 #define H_REG_CRQ 0xFC
433 #define H_FREE_CRQ 0x100
434 #define H_VIO_SIGNAL 0x104
435 #define H_SEND_CRQ 0x108
436 #define H_COPY_RDMA 0x110
437 #define H_REGISTER_LOGICAL_LAN 0x114
438 #define H_FREE_LOGICAL_LAN 0x118
439 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
440 #define H_SEND_LOGICAL_LAN 0x120
441 #define H_BULK_REMOVE 0x124
442 #define H_MULTICAST_CTRL 0x130
443 #define H_SET_XDABR 0x134
444 #define H_STUFF_TCE 0x138
445 #define H_PUT_TCE_INDIRECT 0x13C
446 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
447 #define H_VTERM_PARTNER_INFO 0x150
448 #define H_REGISTER_VTERM 0x154
449 #define H_FREE_VTERM 0x158
450 #define H_RESET_EVENTS 0x15C
451 #define H_ALLOC_RESOURCE 0x160
452 #define H_FREE_RESOURCE 0x164
453 #define H_MODIFY_QP 0x168
454 #define H_QUERY_QP 0x16C
455 #define H_REREGISTER_PMR 0x170
456 #define H_REGISTER_SMR 0x174
457 #define H_QUERY_MR 0x178
458 #define H_QUERY_MW 0x17C
459 #define H_QUERY_HCA 0x180
460 #define H_QUERY_PORT 0x184
461 #define H_MODIFY_PORT 0x188
462 #define H_DEFINE_AQP1 0x18C
463 #define H_GET_TRACE_BUFFER 0x190
464 #define H_DEFINE_AQP0 0x194
465 #define H_RESIZE_MR 0x198
466 #define H_ATTACH_MCQP 0x19C
467 #define H_DETACH_MCQP 0x1A0
468 #define H_CREATE_RPT 0x1A4
469 #define H_REMOVE_RPT 0x1A8
470 #define H_REGISTER_RPAGES 0x1AC
471 #define H_DISABLE_AND_GETC 0x1B0
472 #define H_ERROR_DATA 0x1B4
473 #define H_GET_HCA_INFO 0x1B8
474 #define H_GET_PERF_COUNT 0x1BC
475 #define H_MANAGE_TRACE 0x1C0
476 #define H_GET_CPU_CHARACTERISTICS 0x1C8
477 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
478 #define H_QUERY_INT_STATE 0x1E4
479 #define H_POLL_PENDING 0x1D8
480 #define H_ILLAN_ATTRIBUTES 0x244
481 #define H_MODIFY_HEA_QP 0x250
482 #define H_QUERY_HEA_QP 0x254
483 #define H_QUERY_HEA 0x258
484 #define H_QUERY_HEA_PORT 0x25C
485 #define H_MODIFY_HEA_PORT 0x260
486 #define H_REG_BCMC 0x264
487 #define H_DEREG_BCMC 0x268
488 #define H_REGISTER_HEA_RPAGES 0x26C
489 #define H_DISABLE_AND_GET_HEA 0x270
490 #define H_GET_HEA_INFO 0x274
491 #define H_ALLOC_HEA_RESOURCE 0x278
492 #define H_ADD_CONN 0x284
493 #define H_DEL_CONN 0x288
494 #define H_JOIN 0x298
495 #define H_VASI_STATE 0x2A4
496 #define H_ENABLE_CRQ 0x2B0
497 #define H_GET_EM_PARMS 0x2B8
498 #define H_SET_MPP 0x2D0
499 #define H_GET_MPP 0x2D4
500 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
501 #define H_XIRR_X 0x2FC
502 #define H_RANDOM 0x300
503 #define H_SET_MODE 0x31C
504 #define H_RESIZE_HPT_PREPARE 0x36C
505 #define H_RESIZE_HPT_COMMIT 0x370
506 #define H_CLEAN_SLB 0x374
507 #define H_INVALIDATE_PID 0x378
508 #define H_REGISTER_PROC_TBL 0x37C
509 #define H_SIGNAL_SYS_RESET 0x380
510
511 #define H_INT_GET_SOURCE_INFO 0x3A8
512 #define H_INT_SET_SOURCE_CONFIG 0x3AC
513 #define H_INT_GET_SOURCE_CONFIG 0x3B0
514 #define H_INT_GET_QUEUE_INFO 0x3B4
515 #define H_INT_SET_QUEUE_CONFIG 0x3B8
516 #define H_INT_GET_QUEUE_CONFIG 0x3BC
517 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
518 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
519 #define H_INT_ESB 0x3C8
520 #define H_INT_SYNC 0x3CC
521 #define H_INT_RESET 0x3D0
522 #define H_SCM_READ_METADATA 0x3E4
523 #define H_SCM_WRITE_METADATA 0x3E8
524 #define H_SCM_BIND_MEM 0x3EC
525 #define H_SCM_UNBIND_MEM 0x3F0
526 #define H_SCM_UNBIND_ALL 0x3FC
527
528 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL
529
530 /* The hcalls above are standardized in PAPR and implemented by pHyp
531 * as well.
532 *
533 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
534 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
535 * for "platform-specific" hcalls.
536 */
537 #define KVMPPC_HCALL_BASE 0xf000
538 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
539 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
540 /* Client Architecture support */
541 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
542 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
543 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
544
545 /*
546 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
547 * Secure VM mode via an Ultravisor / Protected Execution Facility
548 */
549 #define SVM_HCALL_BASE 0xEF00
550 #define SVM_H_TPM_COMM 0xEF10
551 #define SVM_HCALL_MAX SVM_H_TPM_COMM
552
553
554 typedef struct SpaprDeviceTreeUpdateHeader {
555 uint32_t version_id;
556 } SpaprDeviceTreeUpdateHeader;
557
558 #define hcall_dprintf(fmt, ...) \
559 do { \
560 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
561 } while (0)
562
563 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
564 target_ulong opcode,
565 target_ulong *args);
566
567 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
568 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
569 target_ulong *args);
570
571 target_ulong do_client_architecture_support(PowerPCCPU *cpu,
572 SpaprMachineState *spapr,
573 target_ulong addr,
574 target_ulong fdt_bufsize);
575
576 /* Virtual Processor Area structure constants */
577 #define VPA_MIN_SIZE 640
578 #define VPA_SIZE_OFFSET 0x4
579 #define VPA_SHARED_PROC_OFFSET 0x9
580 #define VPA_SHARED_PROC_VAL 0x2
581 #define VPA_DISPATCH_COUNTER 0x100
582
583 /* ibm,set-eeh-option */
584 #define RTAS_EEH_DISABLE 0
585 #define RTAS_EEH_ENABLE 1
586 #define RTAS_EEH_THAW_IO 2
587 #define RTAS_EEH_THAW_DMA 3
588
589 /* ibm,get-config-addr-info2 */
590 #define RTAS_GET_PE_ADDR 0
591 #define RTAS_GET_PE_MODE 1
592 #define RTAS_PE_MODE_NONE 0
593 #define RTAS_PE_MODE_NOT_SHARED 1
594 #define RTAS_PE_MODE_SHARED 2
595
596 /* ibm,read-slot-reset-state2 */
597 #define RTAS_EEH_PE_STATE_NORMAL 0
598 #define RTAS_EEH_PE_STATE_RESET 1
599 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
600 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
601 #define RTAS_EEH_PE_STATE_UNAVAIL 5
602 #define RTAS_EEH_NOT_SUPPORT 0
603 #define RTAS_EEH_SUPPORT 1
604 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
605 #define RTAS_EEH_PE_RECOVER_INFO 0
606
607 /* ibm,set-slot-reset */
608 #define RTAS_SLOT_RESET_DEACTIVATE 0
609 #define RTAS_SLOT_RESET_HOT 1
610 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
611
612 /* ibm,slot-error-detail */
613 #define RTAS_SLOT_TEMP_ERR_LOG 1
614 #define RTAS_SLOT_PERM_ERR_LOG 2
615
616 /* RTAS return codes */
617 #define RTAS_OUT_SUCCESS 0
618 #define RTAS_OUT_NO_ERRORS_FOUND 1
619 #define RTAS_OUT_HW_ERROR -1
620 #define RTAS_OUT_BUSY -2
621 #define RTAS_OUT_PARAM_ERROR -3
622 #define RTAS_OUT_NOT_SUPPORTED -3
623 #define RTAS_OUT_NO_SUCH_INDICATOR -3
624 #define RTAS_OUT_NOT_AUTHORIZED -9002
625 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
626
627 /* DDW pagesize mask values from ibm,query-pe-dma-window */
628 #define RTAS_DDW_PGSIZE_4K 0x01
629 #define RTAS_DDW_PGSIZE_64K 0x02
630 #define RTAS_DDW_PGSIZE_16M 0x04
631 #define RTAS_DDW_PGSIZE_32M 0x08
632 #define RTAS_DDW_PGSIZE_64M 0x10
633 #define RTAS_DDW_PGSIZE_128M 0x20
634 #define RTAS_DDW_PGSIZE_256M 0x40
635 #define RTAS_DDW_PGSIZE_16G 0x80
636
637 /* RTAS tokens */
638 #define RTAS_TOKEN_BASE 0x2000
639
640 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
641 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
642 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
643 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
644 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
645 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
646 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
647 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
648 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
649 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
650 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
651 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
652 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
653 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
654 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
655 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
656 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
657 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
658 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
659 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
660 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
661 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
662 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
663 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
664 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
665 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
666 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
667 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
668 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
669 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
670 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
671 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
672 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
673 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
674 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
675 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
676 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
677 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
678 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
679 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
680 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
681 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
682 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A)
683 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
684 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
685
686 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D)
687
688 /* RTAS ibm,get-system-parameter token values */
689 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
690 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
691 #define RTAS_SYSPARM_UUID 48
692
693 /* RTAS indicator/sensor types
694 *
695 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
696 *
697 * NOTE: currently only DR-related sensors are implemented here
698 */
699 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
700 #define RTAS_SENSOR_TYPE_DR 9002
701 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
702 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
703
704 /* Possible values for the platform-processor-diagnostics-run-mode parameter
705 * of the RTAS ibm,get-system-parameter call.
706 */
707 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
708 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
709 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
710 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
711
712 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
713 {
714 return addr & ~0xF000000000000000ULL;
715 }
716
717 static inline uint32_t rtas_ld(target_ulong phys, int n)
718 {
719 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
720 }
721
722 static inline uint64_t rtas_ldq(target_ulong phys, int n)
723 {
724 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
725 }
726
727 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
728 {
729 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
730 }
731
732 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
733 uint32_t token,
734 uint32_t nargs, target_ulong args,
735 uint32_t nret, target_ulong rets);
736 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
737 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
738 uint32_t token, uint32_t nargs, target_ulong args,
739 uint32_t nret, target_ulong rets);
740 void spapr_dt_rtas_tokens(void *fdt, int rtas);
741 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
742
743 #define SPAPR_TCE_PAGE_SHIFT 12
744 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
745 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
746
747 #define SPAPR_VIO_BASE_LIOBN 0x00000000
748 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
749 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
750 (0x80000000 | ((phb_index) << 8) | (window_num))
751 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
752 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
753
754 #define RTAS_SIZE 2048
755 #define RTAS_ERROR_LOG_MAX 2048
756
757 /* Offset from rtas-base where error log is placed */
758 #define RTAS_ERROR_LOG_OFFSET 0x30
759
760 #define RTAS_EVENT_SCAN_RATE 1
761
762 /* This helper should be used to encode interrupt specifiers when the related
763 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
764 * VIO devices, RTAS event sources and PHBs).
765 */
766 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
767 {
768 intspec[0] = cpu_to_be32(irq);
769 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
770 }
771
772 typedef struct SpaprTceTable SpaprTceTable;
773
774 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
775 #define SPAPR_TCE_TABLE(obj) \
776 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE)
777
778 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
779 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
780 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
781
782 struct SpaprTceTable {
783 DeviceState parent;
784 uint32_t liobn;
785 uint32_t nb_table;
786 uint64_t bus_offset;
787 uint32_t page_shift;
788 uint64_t *table;
789 uint32_t mig_nb_table;
790 uint64_t *mig_table;
791 bool bypass;
792 bool need_vfio;
793 bool skipping_replay;
794 int fd;
795 MemoryRegion root;
796 IOMMUMemoryRegion iommu;
797 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
798 QLIST_ENTRY(SpaprTceTable) list;
799 };
800
801 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
802
803 struct SpaprEventLogEntry {
804 uint32_t summary;
805 uint32_t extended_length;
806 void *extended_log;
807 QTAILQ_ENTRY(SpaprEventLogEntry) next;
808 };
809
810 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
811 void spapr_events_init(SpaprMachineState *sm);
812 void spapr_dt_events(SpaprMachineState *sm, void *fdt);
813 void close_htab_fd(SpaprMachineState *spapr);
814 void spapr_setup_hpt(SpaprMachineState *spapr);
815 void spapr_free_hpt(SpaprMachineState *spapr);
816 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
817 void spapr_tce_table_enable(SpaprTceTable *tcet,
818 uint32_t page_shift, uint64_t bus_offset,
819 uint32_t nb_table);
820 void spapr_tce_table_disable(SpaprTceTable *tcet);
821 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
822
823 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
824 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
825 uint32_t liobn, uint64_t window, uint32_t size);
826 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
827 SpaprTceTable *tcet);
828 void spapr_pci_switch_vga(bool big_endian);
829 void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
830 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
831 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
832 uint32_t count);
833 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
834 uint32_t count);
835 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
836 uint32_t count, uint32_t index);
837 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
838 uint32_t count, uint32_t index);
839 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
840 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
841 Error **errp);
842 void spapr_clear_pending_events(SpaprMachineState *spapr);
843 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
844 int spapr_max_server_number(SpaprMachineState *spapr);
845 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
846 uint64_t pte0, uint64_t pte1);
847 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
848
849 /* DRC callbacks. */
850 void spapr_core_release(DeviceState *dev);
851 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
852 void *fdt, int *fdt_start_offset, Error **errp);
853 void spapr_lmb_release(DeviceState *dev);
854 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
855 void *fdt, int *fdt_start_offset, Error **errp);
856 void spapr_phb_release(DeviceState *dev);
857 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
858 void *fdt, int *fdt_start_offset, Error **errp);
859
860 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
861 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
862
863 #define TYPE_SPAPR_RNG "spapr-rng"
864
865 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
866
867 /*
868 * This defines the maximum number of DIMM slots we can have for sPAPR
869 * guest. This is not defined by sPAPR but we are defining it to 32 slots
870 * based on default number of slots provided by PowerPC kernel.
871 */
872 #define SPAPR_MAX_RAM_SLOTS 32
873
874 /* 1GB alignment for hotplug memory region */
875 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
876
877 /*
878 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
879 * property under ibm,dynamic-reconfiguration-memory node.
880 */
881 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
882
883 /*
884 * Defines for flag value in ibm,dynamic-memory property under
885 * ibm,dynamic-reconfiguration-memory node.
886 */
887 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
888 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
889 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
890 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
891
892 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
893
894 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
895
896 int spapr_get_vcpu_id(PowerPCCPU *cpu);
897 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
898 PowerPCCPU *spapr_find_cpu(int vcpu_id);
899
900 int spapr_caps_pre_load(void *opaque);
901 int spapr_caps_pre_save(void *opaque);
902
903 /*
904 * Handling of optional capabilities
905 */
906 extern const VMStateDescription vmstate_spapr_cap_htm;
907 extern const VMStateDescription vmstate_spapr_cap_vsx;
908 extern const VMStateDescription vmstate_spapr_cap_dfp;
909 extern const VMStateDescription vmstate_spapr_cap_cfpc;
910 extern const VMStateDescription vmstate_spapr_cap_sbbc;
911 extern const VMStateDescription vmstate_spapr_cap_ibs;
912 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
913 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
914 extern const VMStateDescription vmstate_spapr_cap_large_decr;
915 extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
916 extern const VMStateDescription vmstate_spapr_cap_fwnmi;
917
918 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
919 {
920 return spapr->eff.caps[cap];
921 }
922
923 void spapr_caps_init(SpaprMachineState *spapr);
924 void spapr_caps_apply(SpaprMachineState *spapr);
925 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
926 void spapr_caps_add_properties(SpaprMachineClass *smc);
927 int spapr_caps_post_migration(SpaprMachineState *spapr);
928
929 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
930 Error **errp);
931 /*
932 * XIVE definitions
933 */
934 #define SPAPR_OV5_XIVE_LEGACY 0x0
935 #define SPAPR_OV5_XIVE_EXPLOIT 0x40
936 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */
937
938 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
939 hwaddr spapr_get_rtas_addr(void);
940 #endif /* HW_SPAPR_H */