include/hw/ppc/spapr.h

   1 #ifndef HW_SPAPR_H
   2 #define HW_SPAPR_H
   3
   4 #include "qemu/units.h"
   5 #include "sysemu/dma.h"
   6 #include "hw/boards.h"
   7 #include "hw/ppc/spapr_drc.h"
   8 #include "hw/mem/pc-dimm.h"
   9 #include "hw/ppc/spapr_ovec.h"
  10 #include "hw/ppc/spapr_irq.h"
  11 #include "hw/ppc/spapr_xive.h"  /* For SpaprXive */
  12 #include "hw/ppc/xics.h"        /* For ICSState */
  13 #include "hw/ppc/spapr_tpm_proxy.h"
  14
  15 struct SpaprVioBus;
  16 struct SpaprPhbState;
  17 struct SpaprNvram;
  18
  19 typedef struct SpaprEventLogEntry SpaprEventLogEntry;
  20 typedef struct SpaprEventSource SpaprEventSource;
  21 typedef struct SpaprPendingHpt SpaprPendingHpt;
  22
  23 #define HPTE64_V_HPTE_DIRTY     0x0000000000000040ULL
  24 #define SPAPR_ENTRY_POINT       0x100
  25
  26 #define SPAPR_TIMEBASE_FREQ     512000000ULL
  27
  28 #define TYPE_SPAPR_RTC "spapr-rtc"
  29
  30 #define SPAPR_RTC(obj)                                  \
  31     OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC)
  32
  33 typedef struct SpaprRtcState SpaprRtcState;
  34 struct SpaprRtcState {
  35     /*< private >*/
  36     DeviceState parent_obj;
  37     int64_t ns_offset;
  38 };
  39
  40 typedef struct SpaprDimmState SpaprDimmState;
  41 typedef struct SpaprMachineClass SpaprMachineClass;
  42
  43 #define TYPE_SPAPR_MACHINE      "spapr-machine"
  44 typedef struct SpaprMachineState SpaprMachineState;
  45 #define SPAPR_MACHINE(obj) \
  46     OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
  47 #define SPAPR_MACHINE_GET_CLASS(obj) \
  48     OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE)
  49 #define SPAPR_MACHINE_CLASS(klass) \
  50     OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE)
  51
  52 typedef enum {
  53     SPAPR_RESIZE_HPT_DEFAULT = 0,
  54     SPAPR_RESIZE_HPT_DISABLED,
  55     SPAPR_RESIZE_HPT_ENABLED,
  56     SPAPR_RESIZE_HPT_REQUIRED,
  57 } SpaprResizeHpt;
  58
  59 /**
  60  * Capabilities
  61  */
  62
  63 /* Hardware Transactional Memory */
  64 #define SPAPR_CAP_HTM                   0x00
  65 /* Vector Scalar Extensions */
  66 #define SPAPR_CAP_VSX                   0x01
  67 /* Decimal Floating Point */
  68 #define SPAPR_CAP_DFP                   0x02
  69 /* Cache Flush on Privilege Change */
  70 #define SPAPR_CAP_CFPC                  0x03
  71 /* Speculation Barrier Bounds Checking */
  72 #define SPAPR_CAP_SBBC                  0x04
  73 /* Indirect Branch Serialisation */
  74 #define SPAPR_CAP_IBS                   0x05
  75 /* HPT Maximum Page Size (encoded as a shift) */
  76 #define SPAPR_CAP_HPT_MAXPAGESIZE       0x06
  77 /* Nested KVM-HV */
  78 #define SPAPR_CAP_NESTED_KVM_HV         0x07
  79 /* Large Decrementer */
  80 #define SPAPR_CAP_LARGE_DECREMENTER     0x08
  81 /* Count Cache Flush Assist HW Instruction */
  82 #define SPAPR_CAP_CCF_ASSIST            0x09
  83 /* Implements PAPR FWNMI option */
  84 #define SPAPR_CAP_FWNMI                 0x0A
  85 /* Num Caps */
  86 #define SPAPR_CAP_NUM                   (SPAPR_CAP_FWNMI + 1)
  87
  88 /*
  89  * Capability Values
  90  */
  91 /* Bool Caps */
  92 #define SPAPR_CAP_OFF                   0x00
  93 #define SPAPR_CAP_ON                    0x01
  94
  95 /* Custom Caps */
  96
  97 /* Generic */
  98 #define SPAPR_CAP_BROKEN                0x00
  99 #define SPAPR_CAP_WORKAROUND            0x01
 100 #define SPAPR_CAP_FIXED                 0x02
 101 /* SPAPR_CAP_IBS (cap-ibs) */
 102 #define SPAPR_CAP_FIXED_IBS             0x02
 103 #define SPAPR_CAP_FIXED_CCD             0x03
 104 #define SPAPR_CAP_FIXED_NA              0x10 /* Lets leave a bit of a gap... */
 105
 106 #define FDT_MAX_SIZE                    0x100000
 107
 108 typedef struct SpaprCapabilities SpaprCapabilities;
 109 struct SpaprCapabilities {
 110     uint8_t caps[SPAPR_CAP_NUM];
 111 };
 112
 113 /**
 114  * SpaprMachineClass:
 115  */
 116 struct SpaprMachineClass {
 117     /*< private >*/
 118     MachineClass parent_class;
 119
 120     /*< public >*/
 121     bool dr_lmb_enabled;       /* enable dynamic-reconfig/hotplug of LMBs */
 122     bool dr_phb_enabled;       /* enable dynamic-reconfig/hotplug of PHBs */
 123     bool update_dt_enabled;    /* enable KVMPPC_H_UPDATE_DT */
 124     bool use_ohci_by_default;  /* use USB-OHCI instead of XHCI */
 125     bool pre_2_10_has_unused_icps;
 126     bool legacy_irq_allocation;
 127     uint32_t nr_xirqs;
 128     bool broken_host_serial_model; /* present real host info to the guest */
 129     bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
 130     bool linux_pci_probe;
 131     bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
 132     hwaddr rma_limit;          /* clamp the RMA to this size */
 133     bool pre_5_1_assoc_refpoints;
 134
 135     void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
 136                           uint64_t *buid, hwaddr *pio,
 137                           hwaddr *mmio32, hwaddr *mmio64,
 138                           unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
 139                           hwaddr *nv2atsd, Error **errp);
 140     SpaprResizeHpt resize_hpt_default;
 141     SpaprCapabilities default_caps;
 142     SpaprIrq *irq;
 143 };
 144
 145 /**
 146  * SpaprMachineState:
 147  */
 148 struct SpaprMachineState {
 149     /*< private >*/
 150     MachineState parent_obj;
 151
 152     struct SpaprVioBus *vio_bus;
 153     QLIST_HEAD(, SpaprPhbState) phbs;
 154     struct SpaprNvram *nvram;
 155     SpaprRtcState rtc;
 156
 157     SpaprResizeHpt resize_hpt;
 158     void *htab;
 159     uint32_t htab_shift;
 160     uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
 161     SpaprPendingHpt *pending_hpt; /* in-progress resize */
 162
 163     hwaddr rma_size;
 164     uint32_t fdt_size;
 165     uint32_t fdt_initial_size;
 166     void *fdt_blob;
 167     long kernel_size;
 168     bool kernel_le;
 169     uint64_t kernel_addr;
 170     uint32_t initrd_base;
 171     long initrd_size;
 172     uint64_t rtc_offset; /* Now used only during incoming migration */
 173     struct PPCTimebase tb;
 174     bool has_graphics;
 175     uint32_t vsmt;       /* Virtual SMT mode (KVM's "core stride") */
 176
 177     Notifier epow_notifier;
 178     QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
 179     bool use_hotplug_event_source;
 180     SpaprEventSource *event_sources;
 181
 182     /* ibm,client-architecture-support option negotiation */
 183     bool cas_pre_isa3_guest;
 184     SpaprOptionVector *ov5;         /* QEMU-supported option vectors */
 185     SpaprOptionVector *ov5_cas;     /* negotiated (via CAS) option vectors */
 186     uint32_t max_compat_pvr;
 187
 188     /* Migration state */
 189     int htab_save_index;
 190     bool htab_first_pass;
 191     int htab_fd;
 192
 193     /* Pending DIMM unplug cache. It is populated when a LMB
 194      * unplug starts. It can be regenerated if a migration
 195      * occurs during the unplug process. */
 196     QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
 197
 198     /* State related to FWNMI option */
 199
 200     /* System Reset and Machine Check Notification Routine addresses
 201      * registered by "ibm,nmi-register" RTAS call.
 202      */
 203     target_ulong fwnmi_system_reset_addr;
 204     target_ulong fwnmi_machine_check_addr;
 205
 206     /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
 207      * set to -1 if a FWNMI machine check is not in progress, else is set to
 208      * the CPU that was delivered the machine check, and is set back to -1
 209      * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
 210      * to synchronize other CPUs.
 211      */
 212     int fwnmi_machine_check_interlock;
 213     QemuCond fwnmi_machine_check_interlock_cond;
 214
 215     /*< public >*/
 216     char *kvm_type;
 217     char *host_model;
 218     char *host_serial;
 219
 220     int32_t irq_map_nr;
 221     unsigned long *irq_map;
 222     SpaprIrq *irq;
 223     qemu_irq *qirqs;
 224     SpaprInterruptController *active_intc;
 225     ICSState *ics;
 226     SpaprXive *xive;
 227
 228     bool cmd_line_caps[SPAPR_CAP_NUM];
 229     SpaprCapabilities def, eff, mig;
 230
 231     unsigned gpu_numa_id;
 232     SpaprTpmProxy *tpm_proxy;
 233
 234     Error *fwnmi_migration_blocker;
 235 };
 236
 237 #define H_SUCCESS         0
 238 #define H_BUSY            1        /* Hardware busy -- retry later */
 239 #define H_CLOSED          2        /* Resource closed */
 240 #define H_NOT_AVAILABLE   3
 241 #define H_CONSTRAINED     4        /* Resource request constrained to max allowed */
 242 #define H_PARTIAL         5
 243 #define H_IN_PROGRESS     14       /* Kind of like busy */
 244 #define H_PAGE_REGISTERED 15
 245 #define H_PARTIAL_STORE   16
 246 #define H_PENDING         17       /* returned from H_POLL_PENDING */
 247 #define H_CONTINUE        18       /* Returned from H_Join on success */
 248 #define H_LONG_BUSY_START_RANGE         9900  /* Start of long busy range */
 249 #define H_LONG_BUSY_ORDER_1_MSEC        9900  /* Long busy, hint that 1msec \
 250                                                  is a good time to retry */
 251 #define H_LONG_BUSY_ORDER_10_MSEC       9901  /* Long busy, hint that 10msec \
 252                                                  is a good time to retry */
 253 #define H_LONG_BUSY_ORDER_100_MSEC      9902  /* Long busy, hint that 100msec \
 254                                                  is a good time to retry */
 255 #define H_LONG_BUSY_ORDER_1_SEC         9903  /* Long busy, hint that 1sec \
 256                                                  is a good time to retry */
 257 #define H_LONG_BUSY_ORDER_10_SEC        9904  /* Long busy, hint that 10sec \
 258                                                  is a good time to retry */
 259 #define H_LONG_BUSY_ORDER_100_SEC       9905  /* Long busy, hint that 100sec \
 260                                                  is a good time to retry */
 261 #define H_LONG_BUSY_END_RANGE           9905  /* End of long busy range */
 262 #define H_HARDWARE        -1       /* Hardware error */
 263 #define H_FUNCTION        -2       /* Function not supported */
 264 #define H_PRIVILEGE       -3       /* Caller not privileged */
 265 #define H_PARAMETER       -4       /* Parameter invalid, out-of-range or conflicting */
 266 #define H_BAD_MODE        -5       /* Illegal msr value */
 267 #define H_PTEG_FULL       -6       /* PTEG is full */
 268 #define H_NOT_FOUND       -7       /* PTE was not found" */
 269 #define H_RESERVED_DABR   -8       /* DABR address is reserved by the hypervisor on this processor" */
 270 #define H_NO_MEM          -9
 271 #define H_AUTHORITY       -10
 272 #define H_PERMISSION      -11
 273 #define H_DROPPED         -12
 274 #define H_SOURCE_PARM     -13
 275 #define H_DEST_PARM       -14
 276 #define H_REMOTE_PARM     -15
 277 #define H_RESOURCE        -16
 278 #define H_ADAPTER_PARM    -17
 279 #define H_RH_PARM         -18
 280 #define H_RCQ_PARM        -19
 281 #define H_SCQ_PARM        -20
 282 #define H_EQ_PARM         -21
 283 #define H_RT_PARM         -22
 284 #define H_ST_PARM         -23
 285 #define H_SIGT_PARM       -24
 286 #define H_TOKEN_PARM      -25
 287 #define H_MLENGTH_PARM    -27
 288 #define H_MEM_PARM        -28
 289 #define H_MEM_ACCESS_PARM -29
 290 #define H_ATTR_PARM       -30
 291 #define H_PORT_PARM       -31
 292 #define H_MCG_PARM        -32
 293 #define H_VL_PARM         -33
 294 #define H_TSIZE_PARM      -34
 295 #define H_TRACE_PARM      -35
 296
 297 #define H_MASK_PARM       -37
 298 #define H_MCG_FULL        -38
 299 #define H_ALIAS_EXIST     -39
 300 #define H_P_COUNTER       -40
 301 #define H_TABLE_FULL      -41
 302 #define H_ALT_TABLE       -42
 303 #define H_MR_CONDITION    -43
 304 #define H_NOT_ENOUGH_RESOURCES -44
 305 #define H_R_STATE         -45
 306 #define H_RESCINDEND      -46
 307 #define H_P2              -55
 308 #define H_P3              -56
 309 #define H_P4              -57
 310 #define H_P5              -58
 311 #define H_P6              -59
 312 #define H_P7              -60
 313 #define H_P8              -61
 314 #define H_P9              -62
 315 #define H_OVERLAP         -68
 316 #define H_UNSUPPORTED_FLAG -256
 317 #define H_MULTI_THREADS_ACTIVE -9005
 318
 319
 320 /* Long Busy is a condition that can be returned by the firmware
 321  * when a call cannot be completed now, but the identical call
 322  * should be retried later.  This prevents calls blocking in the
 323  * firmware for long periods of time.  Annoyingly the firmware can return
 324  * a range of return codes, hinting at how long we should wait before
 325  * retrying.  If you don't care for the hint, the macro below is a good
 326  * way to check for the long_busy return codes
 327  */
 328 #define H_IS_LONG_BUSY(x)  ((x >= H_LONG_BUSY_START_RANGE) \
 329                             && (x <= H_LONG_BUSY_END_RANGE))
 330
 331 /* Flags */
 332 #define H_LARGE_PAGE      (1ULL<<(63-16))
 333 #define H_EXACT           (1ULL<<(63-24))       /* Use exact PTE or return H_PTEG_FULL */
 334 #define H_R_XLATE         (1ULL<<(63-25))       /* include a valid logical page num in the pte if the valid bit is set */
 335 #define H_READ_4          (1ULL<<(63-26))       /* Return 4 PTEs */
 336 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
 337 #define H_PAGE_UNUSED     ((1ULL<<(63-29)) | (1ULL<<(63-30)))
 338 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
 339 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
 340 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
 341 #define H_AVPN            (1ULL<<(63-32))       /* An avpn is provided as a sanity test */
 342 #define H_ANDCOND         (1ULL<<(63-33))
 343 #define H_ICACHE_INVALIDATE (1ULL<<(63-40))     /* icbi, etc.  (ignored for IO pages) */
 344 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41))    /* dcbst, icbi, etc (ignored for IO pages */
 345 #define H_ZERO_PAGE       (1ULL<<(63-48))       /* zero the page before mapping (ignored for IO pages) */
 346 #define H_COPY_PAGE       (1ULL<<(63-49))
 347 #define H_N               (1ULL<<(63-61))
 348 #define H_PP1             (1ULL<<(63-62))
 349 #define H_PP2             (1ULL<<(63-63))
 350
 351 /* Values for 2nd argument to H_SET_MODE */
 352 #define H_SET_MODE_RESOURCE_SET_CIABR           1
 353 #define H_SET_MODE_RESOURCE_SET_DAWR            2
 354 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
 355 #define H_SET_MODE_RESOURCE_LE                  4
 356
 357 /* Flags for H_SET_MODE_RESOURCE_LE */
 358 #define H_SET_MODE_ENDIAN_BIG    0
 359 #define H_SET_MODE_ENDIAN_LITTLE 1
 360
 361 /* VASI States */
 362 #define H_VASI_INVALID    0
 363 #define H_VASI_ENABLED    1
 364 #define H_VASI_ABORTED    2
 365 #define H_VASI_SUSPENDING 3
 366 #define H_VASI_SUSPENDED  4
 367 #define H_VASI_RESUMED    5
 368 #define H_VASI_COMPLETED  6
 369
 370 /* DABRX flags */
 371 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
 372 #define H_DABRX_KERNEL     (1ULL<<(63-62))
 373 #define H_DABRX_USER       (1ULL<<(63-63))
 374
 375 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
 376 #define H_CPU_CHAR_SPEC_BAR_ORI31               PPC_BIT(0)
 377 #define H_CPU_CHAR_BCCTRL_SERIALISED            PPC_BIT(1)
 378 #define H_CPU_CHAR_L1D_FLUSH_ORI30              PPC_BIT(2)
 379 #define H_CPU_CHAR_L1D_FLUSH_TRIG2              PPC_BIT(3)
 380 #define H_CPU_CHAR_L1D_THREAD_PRIV              PPC_BIT(4)
 381 #define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
 382 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
 383 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
 384 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST           PPC_BIT(9)
 385 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
 386 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
 387 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
 388 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE           PPC_BIT(5)
 389
 390 /* Each control block has to be on a 4K boundary */
 391 #define H_CB_ALIGNMENT     4096
 392
 393 /* pSeries hypervisor opcodes */
 394 #define H_REMOVE                0x04
 395 #define H_ENTER                 0x08
 396 #define H_READ                  0x0c
 397 #define H_CLEAR_MOD             0x10
 398 #define H_CLEAR_REF             0x14
 399 #define H_PROTECT               0x18
 400 #define H_GET_TCE               0x1c
 401 #define H_PUT_TCE               0x20
 402 #define H_SET_SPRG0             0x24
 403 #define H_SET_DABR              0x28
 404 #define H_PAGE_INIT             0x2c
 405 #define H_SET_ASR               0x30
 406 #define H_ASR_ON                0x34
 407 #define H_ASR_OFF               0x38
 408 #define H_LOGICAL_CI_LOAD       0x3c
 409 #define H_LOGICAL_CI_STORE      0x40
 410 #define H_LOGICAL_CACHE_LOAD    0x44
 411 #define H_LOGICAL_CACHE_STORE   0x48
 412 #define H_LOGICAL_ICBI          0x4c
 413 #define H_LOGICAL_DCBF          0x50
 414 #define H_GET_TERM_CHAR         0x54
 415 #define H_PUT_TERM_CHAR         0x58
 416 #define H_REAL_TO_LOGICAL       0x5c
 417 #define H_HYPERVISOR_DATA       0x60
 418 #define H_EOI                   0x64
 419 #define H_CPPR                  0x68
 420 #define H_IPI                   0x6c
 421 #define H_IPOLL                 0x70
 422 #define H_XIRR                  0x74
 423 #define H_PERFMON               0x7c
 424 #define H_MIGRATE_DMA           0x78
 425 #define H_REGISTER_VPA          0xDC
 426 #define H_CEDE                  0xE0
 427 #define H_CONFER                0xE4
 428 #define H_PROD                  0xE8
 429 #define H_GET_PPP               0xEC
 430 #define H_SET_PPP               0xF0
 431 #define H_PURR                  0xF4
 432 #define H_PIC                   0xF8
 433 #define H_REG_CRQ               0xFC
 434 #define H_FREE_CRQ              0x100
 435 #define H_VIO_SIGNAL            0x104
 436 #define H_SEND_CRQ              0x108
 437 #define H_COPY_RDMA             0x110
 438 #define H_REGISTER_LOGICAL_LAN  0x114
 439 #define H_FREE_LOGICAL_LAN      0x118
 440 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
 441 #define H_SEND_LOGICAL_LAN      0x120
 442 #define H_BULK_REMOVE           0x124
 443 #define H_MULTICAST_CTRL        0x130
 444 #define H_SET_XDABR             0x134
 445 #define H_STUFF_TCE             0x138
 446 #define H_PUT_TCE_INDIRECT      0x13C
 447 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
 448 #define H_VTERM_PARTNER_INFO    0x150
 449 #define H_REGISTER_VTERM        0x154
 450 #define H_FREE_VTERM            0x158
 451 #define H_RESET_EVENTS          0x15C
 452 #define H_ALLOC_RESOURCE        0x160
 453 #define H_FREE_RESOURCE         0x164
 454 #define H_MODIFY_QP             0x168
 455 #define H_QUERY_QP              0x16C
 456 #define H_REREGISTER_PMR        0x170
 457 #define H_REGISTER_SMR          0x174
 458 #define H_QUERY_MR              0x178
 459 #define H_QUERY_MW              0x17C
 460 #define H_QUERY_HCA             0x180
 461 #define H_QUERY_PORT            0x184
 462 #define H_MODIFY_PORT           0x188
 463 #define H_DEFINE_AQP1           0x18C
 464 #define H_GET_TRACE_BUFFER      0x190
 465 #define H_DEFINE_AQP0           0x194
 466 #define H_RESIZE_MR             0x198
 467 #define H_ATTACH_MCQP           0x19C
 468 #define H_DETACH_MCQP           0x1A0
 469 #define H_CREATE_RPT            0x1A4
 470 #define H_REMOVE_RPT            0x1A8
 471 #define H_REGISTER_RPAGES       0x1AC
 472 #define H_DISABLE_AND_GETC      0x1B0
 473 #define H_ERROR_DATA            0x1B4
 474 #define H_GET_HCA_INFO          0x1B8
 475 #define H_GET_PERF_COUNT        0x1BC
 476 #define H_MANAGE_TRACE          0x1C0
 477 #define H_GET_CPU_CHARACTERISTICS 0x1C8
 478 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
 479 #define H_QUERY_INT_STATE       0x1E4
 480 #define H_POLL_PENDING          0x1D8
 481 #define H_ILLAN_ATTRIBUTES      0x244
 482 #define H_MODIFY_HEA_QP         0x250
 483 #define H_QUERY_HEA_QP          0x254
 484 #define H_QUERY_HEA             0x258
 485 #define H_QUERY_HEA_PORT        0x25C
 486 #define H_MODIFY_HEA_PORT       0x260
 487 #define H_REG_BCMC              0x264
 488 #define H_DEREG_BCMC            0x268
 489 #define H_REGISTER_HEA_RPAGES   0x26C
 490 #define H_DISABLE_AND_GET_HEA   0x270
 491 #define H_GET_HEA_INFO          0x274
 492 #define H_ALLOC_HEA_RESOURCE    0x278
 493 #define H_ADD_CONN              0x284
 494 #define H_DEL_CONN              0x288
 495 #define H_JOIN                  0x298
 496 #define H_VASI_STATE            0x2A4
 497 #define H_ENABLE_CRQ            0x2B0
 498 #define H_GET_EM_PARMS          0x2B8
 499 #define H_SET_MPP               0x2D0
 500 #define H_GET_MPP               0x2D4
 501 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
 502 #define H_XIRR_X                0x2FC
 503 #define H_RANDOM                0x300
 504 #define H_SET_MODE              0x31C
 505 #define H_RESIZE_HPT_PREPARE    0x36C
 506 #define H_RESIZE_HPT_COMMIT     0x370
 507 #define H_CLEAN_SLB             0x374
 508 #define H_INVALIDATE_PID        0x378
 509 #define H_REGISTER_PROC_TBL     0x37C
 510 #define H_SIGNAL_SYS_RESET      0x380
 511
 512 #define H_INT_GET_SOURCE_INFO   0x3A8
 513 #define H_INT_SET_SOURCE_CONFIG 0x3AC
 514 #define H_INT_GET_SOURCE_CONFIG 0x3B0
 515 #define H_INT_GET_QUEUE_INFO    0x3B4
 516 #define H_INT_SET_QUEUE_CONFIG  0x3B8
 517 #define H_INT_GET_QUEUE_CONFIG  0x3BC
 518 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
 519 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
 520 #define H_INT_ESB               0x3C8
 521 #define H_INT_SYNC              0x3CC
 522 #define H_INT_RESET             0x3D0
 523 #define H_SCM_READ_METADATA     0x3E4
 524 #define H_SCM_WRITE_METADATA    0x3E8
 525 #define H_SCM_BIND_MEM          0x3EC
 526 #define H_SCM_UNBIND_MEM        0x3F0
 527 #define H_SCM_UNBIND_ALL        0x3FC
 528
 529 #define MAX_HCALL_OPCODE        H_SCM_UNBIND_ALL
 530
 531 /* The hcalls above are standardized in PAPR and implemented by pHyp
 532  * as well.
 533  *
 534  * We also need some hcalls which are specific to qemu / KVM-on-POWER.
 535  * We put those into the 0xf000-0xfffc range which is reserved by PAPR
 536  * for "platform-specific" hcalls.
 537  */
 538 #define KVMPPC_HCALL_BASE       0xf000
 539 #define KVMPPC_H_RTAS           (KVMPPC_HCALL_BASE + 0x0)
 540 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 541 /* Client Architecture support */
 542 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 543 #define KVMPPC_H_UPDATE_DT      (KVMPPC_HCALL_BASE + 0x3)
 544 #define KVMPPC_HCALL_MAX        KVMPPC_H_UPDATE_DT
 545
 546 /*
 547  * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
 548  * Secure VM mode via an Ultravisor / Protected Execution Facility
 549  */
 550 #define SVM_HCALL_BASE              0xEF00
 551 #define SVM_H_TPM_COMM              0xEF10
 552 #define SVM_HCALL_MAX               SVM_H_TPM_COMM
 553
 554
 555 typedef struct SpaprDeviceTreeUpdateHeader {
 556     uint32_t version_id;
 557 } SpaprDeviceTreeUpdateHeader;
 558
 559 #define hcall_dprintf(fmt, ...) \
 560     do { \
 561         qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
 562     } while (0)
 563
 564 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
 565                                        target_ulong opcode,
 566                                        target_ulong *args);
 567
 568 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
 569 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
 570                              target_ulong *args);
 571
 572 target_ulong do_client_architecture_support(PowerPCCPU *cpu,
 573                                             SpaprMachineState *spapr,
 574                                             target_ulong addr,
 575                                             target_ulong fdt_bufsize);
 576
 577 /* Virtual Processor Area structure constants */
 578 #define VPA_MIN_SIZE           640
 579 #define VPA_SIZE_OFFSET        0x4
 580 #define VPA_SHARED_PROC_OFFSET 0x9
 581 #define VPA_SHARED_PROC_VAL    0x2
 582 #define VPA_DISPATCH_COUNTER   0x100
 583
 584 /* ibm,set-eeh-option */
 585 #define RTAS_EEH_DISABLE                 0
 586 #define RTAS_EEH_ENABLE                  1
 587 #define RTAS_EEH_THAW_IO                 2
 588 #define RTAS_EEH_THAW_DMA                3
 589
 590 /* ibm,get-config-addr-info2 */
 591 #define RTAS_GET_PE_ADDR                 0
 592 #define RTAS_GET_PE_MODE                 1
 593 #define RTAS_PE_MODE_NONE                0
 594 #define RTAS_PE_MODE_NOT_SHARED          1
 595 #define RTAS_PE_MODE_SHARED              2
 596
 597 /* ibm,read-slot-reset-state2 */
 598 #define RTAS_EEH_PE_STATE_NORMAL         0
 599 #define RTAS_EEH_PE_STATE_RESET          1
 600 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
 601 #define RTAS_EEH_PE_STATE_STOPPED_DMA    4
 602 #define RTAS_EEH_PE_STATE_UNAVAIL        5
 603 #define RTAS_EEH_NOT_SUPPORT             0
 604 #define RTAS_EEH_SUPPORT                 1
 605 #define RTAS_EEH_PE_UNAVAIL_INFO         1000
 606 #define RTAS_EEH_PE_RECOVER_INFO         0
 607
 608 /* ibm,set-slot-reset */
 609 #define RTAS_SLOT_RESET_DEACTIVATE       0
 610 #define RTAS_SLOT_RESET_HOT              1
 611 #define RTAS_SLOT_RESET_FUNDAMENTAL      3
 612
 613 /* ibm,slot-error-detail */
 614 #define RTAS_SLOT_TEMP_ERR_LOG           1
 615 #define RTAS_SLOT_PERM_ERR_LOG           2
 616
 617 /* RTAS return codes */
 618 #define RTAS_OUT_SUCCESS                        0
 619 #define RTAS_OUT_NO_ERRORS_FOUND                1
 620 #define RTAS_OUT_HW_ERROR                       -1
 621 #define RTAS_OUT_BUSY                           -2
 622 #define RTAS_OUT_PARAM_ERROR                    -3
 623 #define RTAS_OUT_NOT_SUPPORTED                  -3
 624 #define RTAS_OUT_NO_SUCH_INDICATOR              -3
 625 #define RTAS_OUT_NOT_AUTHORIZED                 -9002
 626 #define RTAS_OUT_SYSPARM_PARAM_ERROR            -9999
 627
 628 /* DDW pagesize mask values from ibm,query-pe-dma-window */
 629 #define RTAS_DDW_PGSIZE_4K       0x01
 630 #define RTAS_DDW_PGSIZE_64K      0x02
 631 #define RTAS_DDW_PGSIZE_16M      0x04
 632 #define RTAS_DDW_PGSIZE_32M      0x08
 633 #define RTAS_DDW_PGSIZE_64M      0x10
 634 #define RTAS_DDW_PGSIZE_128M     0x20
 635 #define RTAS_DDW_PGSIZE_256M     0x40
 636 #define RTAS_DDW_PGSIZE_16G      0x80
 637
 638 /* RTAS tokens */
 639 #define RTAS_TOKEN_BASE      0x2000
 640
 641 #define RTAS_DISPLAY_CHARACTER                  (RTAS_TOKEN_BASE + 0x00)
 642 #define RTAS_GET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x01)
 643 #define RTAS_SET_TIME_OF_DAY                    (RTAS_TOKEN_BASE + 0x02)
 644 #define RTAS_POWER_OFF                          (RTAS_TOKEN_BASE + 0x03)
 645 #define RTAS_SYSTEM_REBOOT                      (RTAS_TOKEN_BASE + 0x04)
 646 #define RTAS_QUERY_CPU_STOPPED_STATE            (RTAS_TOKEN_BASE + 0x05)
 647 #define RTAS_START_CPU                          (RTAS_TOKEN_BASE + 0x06)
 648 #define RTAS_STOP_SELF                          (RTAS_TOKEN_BASE + 0x07)
 649 #define RTAS_IBM_GET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x08)
 650 #define RTAS_IBM_SET_SYSTEM_PARAMETER           (RTAS_TOKEN_BASE + 0x09)
 651 #define RTAS_IBM_SET_XIVE                       (RTAS_TOKEN_BASE + 0x0A)
 652 #define RTAS_IBM_GET_XIVE                       (RTAS_TOKEN_BASE + 0x0B)
 653 #define RTAS_IBM_INT_OFF                        (RTAS_TOKEN_BASE + 0x0C)
 654 #define RTAS_IBM_INT_ON                         (RTAS_TOKEN_BASE + 0x0D)
 655 #define RTAS_CHECK_EXCEPTION                    (RTAS_TOKEN_BASE + 0x0E)
 656 #define RTAS_EVENT_SCAN                         (RTAS_TOKEN_BASE + 0x0F)
 657 #define RTAS_IBM_SET_TCE_BYPASS                 (RTAS_TOKEN_BASE + 0x10)
 658 #define RTAS_QUIESCE                            (RTAS_TOKEN_BASE + 0x11)
 659 #define RTAS_NVRAM_FETCH                        (RTAS_TOKEN_BASE + 0x12)
 660 #define RTAS_NVRAM_STORE                        (RTAS_TOKEN_BASE + 0x13)
 661 #define RTAS_READ_PCI_CONFIG                    (RTAS_TOKEN_BASE + 0x14)
 662 #define RTAS_WRITE_PCI_CONFIG                   (RTAS_TOKEN_BASE + 0x15)
 663 #define RTAS_IBM_READ_PCI_CONFIG                (RTAS_TOKEN_BASE + 0x16)
 664 #define RTAS_IBM_WRITE_PCI_CONFIG               (RTAS_TOKEN_BASE + 0x17)
 665 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER  (RTAS_TOKEN_BASE + 0x18)
 666 #define RTAS_IBM_CHANGE_MSI                     (RTAS_TOKEN_BASE + 0x19)
 667 #define RTAS_SET_INDICATOR                      (RTAS_TOKEN_BASE + 0x1A)
 668 #define RTAS_SET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1B)
 669 #define RTAS_GET_POWER_LEVEL                    (RTAS_TOKEN_BASE + 0x1C)
 670 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 671 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 672 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
 673 #define RTAS_IBM_SET_EEH_OPTION                 (RTAS_TOKEN_BASE + 0x20)
 674 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2          (RTAS_TOKEN_BASE + 0x21)
 675 #define RTAS_IBM_READ_SLOT_RESET_STATE2         (RTAS_TOKEN_BASE + 0x22)
 676 #define RTAS_IBM_SET_SLOT_RESET                 (RTAS_TOKEN_BASE + 0x23)
 677 #define RTAS_IBM_CONFIGURE_PE                   (RTAS_TOKEN_BASE + 0x24)
 678 #define RTAS_IBM_SLOT_ERROR_DETAIL              (RTAS_TOKEN_BASE + 0x25)
 679 #define RTAS_IBM_QUERY_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x26)
 680 #define RTAS_IBM_CREATE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x27)
 681 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW           (RTAS_TOKEN_BASE + 0x28)
 682 #define RTAS_IBM_RESET_PE_DMA_WINDOW            (RTAS_TOKEN_BASE + 0x29)
 683 #define RTAS_IBM_SUSPEND_ME                     (RTAS_TOKEN_BASE + 0x2A)
 684 #define RTAS_IBM_NMI_REGISTER                   (RTAS_TOKEN_BASE + 0x2B)
 685 #define RTAS_IBM_NMI_INTERLOCK                  (RTAS_TOKEN_BASE + 0x2C)
 686
 687 #define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x2D)
 688
 689 /* RTAS ibm,get-system-parameter token values */
 690 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20
 691 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE        42
 692 #define RTAS_SYSPARM_UUID                        48
 693
 694 /* RTAS indicator/sensor types
 695  *
 696  * as defined by PAPR+ 2.7 7.3.5.4, Table 41
 697  *
 698  * NOTE: currently only DR-related sensors are implemented here
 699  */
 700 #define RTAS_SENSOR_TYPE_ISOLATION_STATE        9001
 701 #define RTAS_SENSOR_TYPE_DR                     9002
 702 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE       9003
 703 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
 704
 705 /* Possible values for the platform-processor-diagnostics-run-mode parameter
 706  * of the RTAS ibm,get-system-parameter call.
 707  */
 708 #define DIAGNOSTICS_RUN_MODE_DISABLED  0
 709 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
 710 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
 711 #define DIAGNOSTICS_RUN_MODE_PERIODIC  3
 712
 713 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
 714 {
 715     return addr & ~0xF000000000000000ULL;
 716 }
 717
 718 static inline uint32_t rtas_ld(target_ulong phys, int n)
 719 {
 720     return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
 721 }
 722
 723 static inline uint64_t rtas_ldq(target_ulong phys, int n)
 724 {
 725     return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
 726 }
 727
 728 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
 729 {
 730     stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
 731 }
 732
 733 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
 734                               uint32_t token,
 735                               uint32_t nargs, target_ulong args,
 736                               uint32_t nret, target_ulong rets);
 737 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
 738 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
 739                              uint32_t token, uint32_t nargs, target_ulong args,
 740                              uint32_t nret, target_ulong rets);
 741 void spapr_dt_rtas_tokens(void *fdt, int rtas);
 742 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
 743
 744 #define SPAPR_TCE_PAGE_SHIFT   12
 745 #define SPAPR_TCE_PAGE_SIZE    (1ULL << SPAPR_TCE_PAGE_SHIFT)
 746 #define SPAPR_TCE_PAGE_MASK    (SPAPR_TCE_PAGE_SIZE - 1)
 747
 748 #define SPAPR_VIO_BASE_LIOBN    0x00000000
 749 #define SPAPR_VIO_LIOBN(reg)    (0x00000000 | (reg))
 750 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
 751     (0x80000000 | ((phb_index) << 8) | (window_num))
 752 #define SPAPR_IS_PCI_LIOBN(liobn)   (!!((liobn) & 0x80000000))
 753 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
 754
 755 #define RTAS_SIZE               2048
 756 #define RTAS_ERROR_LOG_MAX      2048
 757
 758 /* Offset from rtas-base where error log is placed */
 759 #define RTAS_ERROR_LOG_OFFSET       0x30
 760
 761 #define RTAS_EVENT_SCAN_RATE    1
 762
 763 /* This helper should be used to encode interrupt specifiers when the related
 764  * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
 765  * VIO devices, RTAS event sources and PHBs).
 766  */
 767 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
 768 {
 769     intspec[0] = cpu_to_be32(irq);
 770     intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
 771 }
 772
 773 typedef struct SpaprTceTable SpaprTceTable;
 774
 775 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
 776 #define SPAPR_TCE_TABLE(obj) \
 777     OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE)
 778
 779 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
 780 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
 781         OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
 782
 783 struct SpaprTceTable {
 784     DeviceState parent;
 785     uint32_t liobn;
 786     uint32_t nb_table;
 787     uint64_t bus_offset;
 788     uint32_t page_shift;
 789     uint64_t *table;
 790     uint32_t mig_nb_table;
 791     uint64_t *mig_table;
 792     bool bypass;
 793     bool need_vfio;
 794     bool skipping_replay;
 795     int fd;
 796     MemoryRegion root;
 797     IOMMUMemoryRegion iommu;
 798     struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
 799     QLIST_ENTRY(SpaprTceTable) list;
 800 };
 801
 802 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
 803
 804 struct SpaprEventLogEntry {
 805     uint32_t summary;
 806     uint32_t extended_length;
 807     void *extended_log;
 808     QTAILQ_ENTRY(SpaprEventLogEntry) next;
 809 };
 810
 811 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
 812 void spapr_events_init(SpaprMachineState *sm);
 813 void spapr_dt_events(SpaprMachineState *sm, void *fdt);
 814 void close_htab_fd(SpaprMachineState *spapr);
 815 void spapr_setup_hpt(SpaprMachineState *spapr);
 816 void spapr_free_hpt(SpaprMachineState *spapr);
 817 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
 818 void spapr_tce_table_enable(SpaprTceTable *tcet,
 819                             uint32_t page_shift, uint64_t bus_offset,
 820                             uint32_t nb_table);
 821 void spapr_tce_table_disable(SpaprTceTable *tcet);
 822 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
 823
 824 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
 825 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 826                  uint32_t liobn, uint64_t window, uint32_t size);
 827 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
 828                       SpaprTceTable *tcet);
 829 void spapr_pci_switch_vga(bool big_endian);
 830 void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
 831 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
 832 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
 833                                        uint32_t count);
 834 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
 835                                           uint32_t count);
 836 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
 837                                             uint32_t count, uint32_t index);
 838 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
 839                                                uint32_t count, uint32_t index);
 840 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
 841 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
 842                           Error **errp);
 843 void spapr_clear_pending_events(SpaprMachineState *spapr);
 844 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
 845 int spapr_max_server_number(SpaprMachineState *spapr);
 846 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
 847                       uint64_t pte0, uint64_t pte1);
 848 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
 849
 850 /* DRC callbacks. */
 851 void spapr_core_release(DeviceState *dev);
 852 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 853                            void *fdt, int *fdt_start_offset, Error **errp);
 854 void spapr_lmb_release(DeviceState *dev);
 855 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 856                           void *fdt, int *fdt_start_offset, Error **errp);
 857 void spapr_phb_release(DeviceState *dev);
 858 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
 859                           void *fdt, int *fdt_start_offset, Error **errp);
 860
 861 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
 862 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
 863
 864 #define TYPE_SPAPR_RNG "spapr-rng"
 865
 866 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
 867
 868 /*
 869  * This defines the maximum number of DIMM slots we can have for sPAPR
 870  * guest. This is not defined by sPAPR but we are defining it to 32 slots
 871  * based on default number of slots provided by PowerPC kernel.
 872  */
 873 #define SPAPR_MAX_RAM_SLOTS     32
 874
 875 /* 1GB alignment for hotplug memory region */
 876 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
 877
 878 /*
 879  * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
 880  * property under ibm,dynamic-reconfiguration-memory node.
 881  */
 882 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
 883
 884 /*
 885  * Defines for flag value in ibm,dynamic-memory property under
 886  * ibm,dynamic-reconfiguration-memory node.
 887  */
 888 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
 889 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
 890 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
 891 #define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100
 892
 893 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
 894
 895 #define HTAB_SIZE(spapr)        (1ULL << ((spapr)->htab_shift))
 896
 897 int spapr_get_vcpu_id(PowerPCCPU *cpu);
 898 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
 899 PowerPCCPU *spapr_find_cpu(int vcpu_id);
 900
 901 int spapr_caps_pre_load(void *opaque);
 902 int spapr_caps_pre_save(void *opaque);
 903
 904 /*
 905  * Handling of optional capabilities
 906  */
 907 extern const VMStateDescription vmstate_spapr_cap_htm;
 908 extern const VMStateDescription vmstate_spapr_cap_vsx;
 909 extern const VMStateDescription vmstate_spapr_cap_dfp;
 910 extern const VMStateDescription vmstate_spapr_cap_cfpc;
 911 extern const VMStateDescription vmstate_spapr_cap_sbbc;
 912 extern const VMStateDescription vmstate_spapr_cap_ibs;
 913 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
 914 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
 915 extern const VMStateDescription vmstate_spapr_cap_large_decr;
 916 extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
 917 extern const VMStateDescription vmstate_spapr_cap_fwnmi;
 918
 919 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
 920 {
 921     return spapr->eff.caps[cap];
 922 }
 923
 924 void spapr_caps_init(SpaprMachineState *spapr);
 925 void spapr_caps_apply(SpaprMachineState *spapr);
 926 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
 927 void spapr_caps_add_properties(SpaprMachineClass *smc);
 928 int spapr_caps_post_migration(SpaprMachineState *spapr);
 929
 930 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
 931                           Error **errp);
 932 /*
 933  * XIVE definitions
 934  */
 935 #define SPAPR_OV5_XIVE_LEGACY   0x0
 936 #define SPAPR_OV5_XIVE_EXPLOIT  0x40
 937 #define SPAPR_OV5_XIVE_BOTH     0x80 /* Only to advertise on the platform */
 938
 939 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
 940 hwaddr spapr_get_rtas_addr(void);
 941 #endif /* HW_SPAPR_H */