ppc/spapr: QOM'ify sPAPRRTCState
[qemu.git] / include / hw / ppc / spapr.h
1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3
4 #include "sysemu/dma.h"
5 #include "hw/boards.h"
6 #include "hw/ppc/xics.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10
11 struct VIOsPAPRBus;
12 struct sPAPRPHBState;
13 struct sPAPRNVRAM;
14 typedef struct sPAPRConfigureConnectorState sPAPRConfigureConnectorState;
15 typedef struct sPAPREventLogEntry sPAPREventLogEntry;
16 typedef struct sPAPREventSource sPAPREventSource;
17
18 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
19 #define SPAPR_ENTRY_POINT 0x100
20
21 #define SPAPR_TIMEBASE_FREQ 512000000ULL
22
23 #define TYPE_SPAPR_RTC "spapr-rtc"
24
25 #define SPAPR_RTC(obj) \
26 OBJECT_CHECK(sPAPRRTCState, (obj), TYPE_SPAPR_RTC)
27
28 typedef struct sPAPRRTCState sPAPRRTCState;
29 struct sPAPRRTCState {
30 /*< private >*/
31 DeviceState parent_obj;
32 int64_t ns_offset;
33 };
34
35 typedef struct sPAPRMachineClass sPAPRMachineClass;
36
37 #define TYPE_SPAPR_MACHINE "spapr-machine"
38 #define SPAPR_MACHINE(obj) \
39 OBJECT_CHECK(sPAPRMachineState, (obj), TYPE_SPAPR_MACHINE)
40 #define SPAPR_MACHINE_GET_CLASS(obj) \
41 OBJECT_GET_CLASS(sPAPRMachineClass, obj, TYPE_SPAPR_MACHINE)
42 #define SPAPR_MACHINE_CLASS(klass) \
43 OBJECT_CLASS_CHECK(sPAPRMachineClass, klass, TYPE_SPAPR_MACHINE)
44
45 /**
46 * sPAPRMachineClass:
47 */
48 struct sPAPRMachineClass {
49 /*< private >*/
50 MachineClass parent_class;
51
52 /*< public >*/
53 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
54 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
55 const char *tcg_default_cpu; /* which (TCG) CPU to simulate by default */
56 void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index,
57 uint64_t *buid, hwaddr *pio,
58 hwaddr *mmio32, hwaddr *mmio64,
59 unsigned n_dma, uint32_t *liobns, Error **errp);
60 };
61
62 /**
63 * sPAPRMachineState:
64 */
65 struct sPAPRMachineState {
66 /*< private >*/
67 MachineState parent_obj;
68
69 struct VIOsPAPRBus *vio_bus;
70 QLIST_HEAD(, sPAPRPHBState) phbs;
71 struct sPAPRNVRAM *nvram;
72 ICSState *ics;
73 sPAPRRTCState rtc;
74
75 void *htab;
76 uint32_t htab_shift;
77 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
78 hwaddr rma_size;
79 int vrma_adjust;
80 ssize_t rtas_size;
81 void *rtas_blob;
82 long kernel_size;
83 bool kernel_le;
84 uint32_t initrd_base;
85 long initrd_size;
86 uint64_t rtc_offset; /* Now used only during incoming migration */
87 struct PPCTimebase tb;
88 bool has_graphics;
89 sPAPROptionVector *ov5; /* QEMU-supported option vectors */
90 sPAPROptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
91 bool cas_reboot;
92
93 Notifier epow_notifier;
94 QTAILQ_HEAD(, sPAPREventLogEntry) pending_events;
95 bool use_hotplug_event_source;
96 sPAPREventSource *event_sources;
97
98 /* Migration state */
99 int htab_save_index;
100 bool htab_first_pass;
101 int htab_fd;
102
103 /* RTAS state */
104 QTAILQ_HEAD(, sPAPRConfigureConnectorState) ccs_list;
105
106 /*< public >*/
107 char *kvm_type;
108 MemoryHotplugState hotplug_memory;
109
110 uint32_t nr_servers;
111 ICPState *icps;
112 };
113
114 #define H_SUCCESS 0
115 #define H_BUSY 1 /* Hardware busy -- retry later */
116 #define H_CLOSED 2 /* Resource closed */
117 #define H_NOT_AVAILABLE 3
118 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
119 #define H_PARTIAL 5
120 #define H_IN_PROGRESS 14 /* Kind of like busy */
121 #define H_PAGE_REGISTERED 15
122 #define H_PARTIAL_STORE 16
123 #define H_PENDING 17 /* returned from H_POLL_PENDING */
124 #define H_CONTINUE 18 /* Returned from H_Join on success */
125 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
126 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
127 is a good time to retry */
128 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
129 is a good time to retry */
130 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
131 is a good time to retry */
132 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
133 is a good time to retry */
134 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
135 is a good time to retry */
136 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
137 is a good time to retry */
138 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
139 #define H_HARDWARE -1 /* Hardware error */
140 #define H_FUNCTION -2 /* Function not supported */
141 #define H_PRIVILEGE -3 /* Caller not privileged */
142 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
143 #define H_BAD_MODE -5 /* Illegal msr value */
144 #define H_PTEG_FULL -6 /* PTEG is full */
145 #define H_NOT_FOUND -7 /* PTE was not found" */
146 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
147 #define H_NO_MEM -9
148 #define H_AUTHORITY -10
149 #define H_PERMISSION -11
150 #define H_DROPPED -12
151 #define H_SOURCE_PARM -13
152 #define H_DEST_PARM -14
153 #define H_REMOTE_PARM -15
154 #define H_RESOURCE -16
155 #define H_ADAPTER_PARM -17
156 #define H_RH_PARM -18
157 #define H_RCQ_PARM -19
158 #define H_SCQ_PARM -20
159 #define H_EQ_PARM -21
160 #define H_RT_PARM -22
161 #define H_ST_PARM -23
162 #define H_SIGT_PARM -24
163 #define H_TOKEN_PARM -25
164 #define H_MLENGTH_PARM -27
165 #define H_MEM_PARM -28
166 #define H_MEM_ACCESS_PARM -29
167 #define H_ATTR_PARM -30
168 #define H_PORT_PARM -31
169 #define H_MCG_PARM -32
170 #define H_VL_PARM -33
171 #define H_TSIZE_PARM -34
172 #define H_TRACE_PARM -35
173
174 #define H_MASK_PARM -37
175 #define H_MCG_FULL -38
176 #define H_ALIAS_EXIST -39
177 #define H_P_COUNTER -40
178 #define H_TABLE_FULL -41
179 #define H_ALT_TABLE -42
180 #define H_MR_CONDITION -43
181 #define H_NOT_ENOUGH_RESOURCES -44
182 #define H_R_STATE -45
183 #define H_RESCINDEND -46
184 #define H_P2 -55
185 #define H_P3 -56
186 #define H_P4 -57
187 #define H_P5 -58
188 #define H_P6 -59
189 #define H_P7 -60
190 #define H_P8 -61
191 #define H_P9 -62
192 #define H_UNSUPPORTED_FLAG -256
193 #define H_MULTI_THREADS_ACTIVE -9005
194
195
196 /* Long Busy is a condition that can be returned by the firmware
197 * when a call cannot be completed now, but the identical call
198 * should be retried later. This prevents calls blocking in the
199 * firmware for long periods of time. Annoyingly the firmware can return
200 * a range of return codes, hinting at how long we should wait before
201 * retrying. If you don't care for the hint, the macro below is a good
202 * way to check for the long_busy return codes
203 */
204 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
205 && (x <= H_LONG_BUSY_END_RANGE))
206
207 /* Flags */
208 #define H_LARGE_PAGE (1ULL<<(63-16))
209 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
210 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
211 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
212 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
213 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
214 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
215 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
216 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
217 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
218 #define H_ANDCOND (1ULL<<(63-33))
219 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
220 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
221 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
222 #define H_COPY_PAGE (1ULL<<(63-49))
223 #define H_N (1ULL<<(63-61))
224 #define H_PP1 (1ULL<<(63-62))
225 #define H_PP2 (1ULL<<(63-63))
226
227 /* Values for 2nd argument to H_SET_MODE */
228 #define H_SET_MODE_RESOURCE_SET_CIABR 1
229 #define H_SET_MODE_RESOURCE_SET_DAWR 2
230 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
231 #define H_SET_MODE_RESOURCE_LE 4
232
233 /* Flags for H_SET_MODE_RESOURCE_LE */
234 #define H_SET_MODE_ENDIAN_BIG 0
235 #define H_SET_MODE_ENDIAN_LITTLE 1
236
237 /* VASI States */
238 #define H_VASI_INVALID 0
239 #define H_VASI_ENABLED 1
240 #define H_VASI_ABORTED 2
241 #define H_VASI_SUSPENDING 3
242 #define H_VASI_SUSPENDED 4
243 #define H_VASI_RESUMED 5
244 #define H_VASI_COMPLETED 6
245
246 /* DABRX flags */
247 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
248 #define H_DABRX_KERNEL (1ULL<<(63-62))
249 #define H_DABRX_USER (1ULL<<(63-63))
250
251 /* Each control block has to be on a 4K boundary */
252 #define H_CB_ALIGNMENT 4096
253
254 /* pSeries hypervisor opcodes */
255 #define H_REMOVE 0x04
256 #define H_ENTER 0x08
257 #define H_READ 0x0c
258 #define H_CLEAR_MOD 0x10
259 #define H_CLEAR_REF 0x14
260 #define H_PROTECT 0x18
261 #define H_GET_TCE 0x1c
262 #define H_PUT_TCE 0x20
263 #define H_SET_SPRG0 0x24
264 #define H_SET_DABR 0x28
265 #define H_PAGE_INIT 0x2c
266 #define H_SET_ASR 0x30
267 #define H_ASR_ON 0x34
268 #define H_ASR_OFF 0x38
269 #define H_LOGICAL_CI_LOAD 0x3c
270 #define H_LOGICAL_CI_STORE 0x40
271 #define H_LOGICAL_CACHE_LOAD 0x44
272 #define H_LOGICAL_CACHE_STORE 0x48
273 #define H_LOGICAL_ICBI 0x4c
274 #define H_LOGICAL_DCBF 0x50
275 #define H_GET_TERM_CHAR 0x54
276 #define H_PUT_TERM_CHAR 0x58
277 #define H_REAL_TO_LOGICAL 0x5c
278 #define H_HYPERVISOR_DATA 0x60
279 #define H_EOI 0x64
280 #define H_CPPR 0x68
281 #define H_IPI 0x6c
282 #define H_IPOLL 0x70
283 #define H_XIRR 0x74
284 #define H_PERFMON 0x7c
285 #define H_MIGRATE_DMA 0x78
286 #define H_REGISTER_VPA 0xDC
287 #define H_CEDE 0xE0
288 #define H_CONFER 0xE4
289 #define H_PROD 0xE8
290 #define H_GET_PPP 0xEC
291 #define H_SET_PPP 0xF0
292 #define H_PURR 0xF4
293 #define H_PIC 0xF8
294 #define H_REG_CRQ 0xFC
295 #define H_FREE_CRQ 0x100
296 #define H_VIO_SIGNAL 0x104
297 #define H_SEND_CRQ 0x108
298 #define H_COPY_RDMA 0x110
299 #define H_REGISTER_LOGICAL_LAN 0x114
300 #define H_FREE_LOGICAL_LAN 0x118
301 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
302 #define H_SEND_LOGICAL_LAN 0x120
303 #define H_BULK_REMOVE 0x124
304 #define H_MULTICAST_CTRL 0x130
305 #define H_SET_XDABR 0x134
306 #define H_STUFF_TCE 0x138
307 #define H_PUT_TCE_INDIRECT 0x13C
308 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
309 #define H_VTERM_PARTNER_INFO 0x150
310 #define H_REGISTER_VTERM 0x154
311 #define H_FREE_VTERM 0x158
312 #define H_RESET_EVENTS 0x15C
313 #define H_ALLOC_RESOURCE 0x160
314 #define H_FREE_RESOURCE 0x164
315 #define H_MODIFY_QP 0x168
316 #define H_QUERY_QP 0x16C
317 #define H_REREGISTER_PMR 0x170
318 #define H_REGISTER_SMR 0x174
319 #define H_QUERY_MR 0x178
320 #define H_QUERY_MW 0x17C
321 #define H_QUERY_HCA 0x180
322 #define H_QUERY_PORT 0x184
323 #define H_MODIFY_PORT 0x188
324 #define H_DEFINE_AQP1 0x18C
325 #define H_GET_TRACE_BUFFER 0x190
326 #define H_DEFINE_AQP0 0x194
327 #define H_RESIZE_MR 0x198
328 #define H_ATTACH_MCQP 0x19C
329 #define H_DETACH_MCQP 0x1A0
330 #define H_CREATE_RPT 0x1A4
331 #define H_REMOVE_RPT 0x1A8
332 #define H_REGISTER_RPAGES 0x1AC
333 #define H_DISABLE_AND_GETC 0x1B0
334 #define H_ERROR_DATA 0x1B4
335 #define H_GET_HCA_INFO 0x1B8
336 #define H_GET_PERF_COUNT 0x1BC
337 #define H_MANAGE_TRACE 0x1C0
338 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
339 #define H_QUERY_INT_STATE 0x1E4
340 #define H_POLL_PENDING 0x1D8
341 #define H_ILLAN_ATTRIBUTES 0x244
342 #define H_MODIFY_HEA_QP 0x250
343 #define H_QUERY_HEA_QP 0x254
344 #define H_QUERY_HEA 0x258
345 #define H_QUERY_HEA_PORT 0x25C
346 #define H_MODIFY_HEA_PORT 0x260
347 #define H_REG_BCMC 0x264
348 #define H_DEREG_BCMC 0x268
349 #define H_REGISTER_HEA_RPAGES 0x26C
350 #define H_DISABLE_AND_GET_HEA 0x270
351 #define H_GET_HEA_INFO 0x274
352 #define H_ALLOC_HEA_RESOURCE 0x278
353 #define H_ADD_CONN 0x284
354 #define H_DEL_CONN 0x288
355 #define H_JOIN 0x298
356 #define H_VASI_STATE 0x2A4
357 #define H_ENABLE_CRQ 0x2B0
358 #define H_GET_EM_PARMS 0x2B8
359 #define H_SET_MPP 0x2D0
360 #define H_GET_MPP 0x2D4
361 #define H_XIRR_X 0x2FC
362 #define H_RANDOM 0x300
363 #define H_SET_MODE 0x31C
364 #define H_SIGNAL_SYS_RESET 0x380
365 #define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
366
367 /* The hcalls above are standardized in PAPR and implemented by pHyp
368 * as well.
369 *
370 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
371 * So far we just need one for H_RTAS, but in future we'll need more
372 * for extensions like virtio. We put those into the 0xf000-0xfffc
373 * range which is reserved by PAPR for "platform-specific" hcalls.
374 */
375 #define KVMPPC_HCALL_BASE 0xf000
376 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
377 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
378 /* Client Architecture support */
379 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
380 #define KVMPPC_HCALL_MAX KVMPPC_H_CAS
381
382 typedef struct sPAPRDeviceTreeUpdateHeader {
383 uint32_t version_id;
384 } sPAPRDeviceTreeUpdateHeader;
385
386 #define hcall_dprintf(fmt, ...) \
387 do { \
388 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
389 } while (0)
390
391 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
392 target_ulong opcode,
393 target_ulong *args);
394
395 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
396 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
397 target_ulong *args);
398
399 /* ibm,set-eeh-option */
400 #define RTAS_EEH_DISABLE 0
401 #define RTAS_EEH_ENABLE 1
402 #define RTAS_EEH_THAW_IO 2
403 #define RTAS_EEH_THAW_DMA 3
404
405 /* ibm,get-config-addr-info2 */
406 #define RTAS_GET_PE_ADDR 0
407 #define RTAS_GET_PE_MODE 1
408 #define RTAS_PE_MODE_NONE 0
409 #define RTAS_PE_MODE_NOT_SHARED 1
410 #define RTAS_PE_MODE_SHARED 2
411
412 /* ibm,read-slot-reset-state2 */
413 #define RTAS_EEH_PE_STATE_NORMAL 0
414 #define RTAS_EEH_PE_STATE_RESET 1
415 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
416 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
417 #define RTAS_EEH_PE_STATE_UNAVAIL 5
418 #define RTAS_EEH_NOT_SUPPORT 0
419 #define RTAS_EEH_SUPPORT 1
420 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
421 #define RTAS_EEH_PE_RECOVER_INFO 0
422
423 /* ibm,set-slot-reset */
424 #define RTAS_SLOT_RESET_DEACTIVATE 0
425 #define RTAS_SLOT_RESET_HOT 1
426 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
427
428 /* ibm,slot-error-detail */
429 #define RTAS_SLOT_TEMP_ERR_LOG 1
430 #define RTAS_SLOT_PERM_ERR_LOG 2
431
432 /* RTAS return codes */
433 #define RTAS_OUT_SUCCESS 0
434 #define RTAS_OUT_NO_ERRORS_FOUND 1
435 #define RTAS_OUT_HW_ERROR -1
436 #define RTAS_OUT_BUSY -2
437 #define RTAS_OUT_PARAM_ERROR -3
438 #define RTAS_OUT_NOT_SUPPORTED -3
439 #define RTAS_OUT_NO_SUCH_INDICATOR -3
440 #define RTAS_OUT_NOT_AUTHORIZED -9002
441 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
442
443 /* DDW pagesize mask values from ibm,query-pe-dma-window */
444 #define RTAS_DDW_PGSIZE_4K 0x01
445 #define RTAS_DDW_PGSIZE_64K 0x02
446 #define RTAS_DDW_PGSIZE_16M 0x04
447 #define RTAS_DDW_PGSIZE_32M 0x08
448 #define RTAS_DDW_PGSIZE_64M 0x10
449 #define RTAS_DDW_PGSIZE_128M 0x20
450 #define RTAS_DDW_PGSIZE_256M 0x40
451 #define RTAS_DDW_PGSIZE_16G 0x80
452
453 /* RTAS tokens */
454 #define RTAS_TOKEN_BASE 0x2000
455
456 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
457 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
458 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
459 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
460 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
461 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
462 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
463 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
464 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
465 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
466 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
467 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
468 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
469 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
470 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
471 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
472 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
473 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
474 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
475 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
476 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
477 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
478 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
479 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
480 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
481 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
482 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
483 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
484 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
485 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
486 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
487 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
488 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
489 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
490 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
491 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
492 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
493 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
494 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
495 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
496 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
497 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
498
499 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2A)
500
501 /* RTAS ibm,get-system-parameter token values */
502 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
503 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
504 #define RTAS_SYSPARM_UUID 48
505
506 /* RTAS indicator/sensor types
507 *
508 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
509 *
510 * NOTE: currently only DR-related sensors are implemented here
511 */
512 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
513 #define RTAS_SENSOR_TYPE_DR 9002
514 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
515 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
516
517 /* Possible values for the platform-processor-diagnostics-run-mode parameter
518 * of the RTAS ibm,get-system-parameter call.
519 */
520 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
521 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
522 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
523 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
524
525 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
526 {
527 return addr & ~0xF000000000000000ULL;
528 }
529
530 static inline uint32_t rtas_ld(target_ulong phys, int n)
531 {
532 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
533 }
534
535 static inline uint64_t rtas_ldq(target_ulong phys, int n)
536 {
537 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
538 }
539
540 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
541 {
542 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
543 }
544
545 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, sPAPRMachineState *sm,
546 uint32_t token,
547 uint32_t nargs, target_ulong args,
548 uint32_t nret, target_ulong rets);
549 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
550 target_ulong spapr_rtas_call(PowerPCCPU *cpu, sPAPRMachineState *sm,
551 uint32_t token, uint32_t nargs, target_ulong args,
552 uint32_t nret, target_ulong rets);
553 void spapr_dt_rtas_tokens(void *fdt, int rtas);
554 void spapr_load_rtas(sPAPRMachineState *spapr, void *fdt, hwaddr addr);
555
556 #define SPAPR_TCE_PAGE_SHIFT 12
557 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
558 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
559
560 #define SPAPR_VIO_BASE_LIOBN 0x00000000
561 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
562 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
563 (0x80000000 | ((phb_index) << 8) | (window_num))
564 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
565 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
566
567 #define RTAS_ERROR_LOG_MAX 2048
568
569 #define RTAS_EVENT_SCAN_RATE 1
570
571 typedef struct sPAPRTCETable sPAPRTCETable;
572
573 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
574 #define SPAPR_TCE_TABLE(obj) \
575 OBJECT_CHECK(sPAPRTCETable, (obj), TYPE_SPAPR_TCE_TABLE)
576
577 struct sPAPRTCETable {
578 DeviceState parent;
579 uint32_t liobn;
580 uint32_t nb_table;
581 uint64_t bus_offset;
582 uint32_t page_shift;
583 uint64_t *table;
584 uint32_t mig_nb_table;
585 uint64_t *mig_table;
586 bool bypass;
587 bool need_vfio;
588 int fd;
589 MemoryRegion root, iommu;
590 struct VIOsPAPRDevice *vdev; /* for @bypass migration compatibility only */
591 QLIST_ENTRY(sPAPRTCETable) list;
592 };
593
594 sPAPRTCETable *spapr_tce_find_by_liobn(target_ulong liobn);
595
596 struct sPAPREventLogEntry {
597 int log_type;
598 bool exception;
599 void *data;
600 QTAILQ_ENTRY(sPAPREventLogEntry) next;
601 };
602
603 void spapr_events_init(sPAPRMachineState *sm);
604 void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
605 int spapr_h_cas_compose_response(sPAPRMachineState *sm,
606 target_ulong addr, target_ulong size,
607 sPAPROptionVector *ov5_updates);
608 sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
609 void spapr_tce_table_enable(sPAPRTCETable *tcet,
610 uint32_t page_shift, uint64_t bus_offset,
611 uint32_t nb_table);
612 void spapr_tce_table_disable(sPAPRTCETable *tcet);
613 void spapr_tce_set_need_vfio(sPAPRTCETable *tcet, bool need_vfio);
614
615 MemoryRegion *spapr_tce_get_iommu(sPAPRTCETable *tcet);
616 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
617 uint32_t liobn, uint64_t window, uint32_t size);
618 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
619 sPAPRTCETable *tcet);
620 void spapr_pci_switch_vga(bool big_endian);
621 void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc);
622 void spapr_hotplug_req_remove_by_index(sPAPRDRConnector *drc);
623 void spapr_hotplug_req_add_by_count(sPAPRDRConnectorType drc_type,
624 uint32_t count);
625 void spapr_hotplug_req_remove_by_count(sPAPRDRConnectorType drc_type,
626 uint32_t count);
627 void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
628 uint32_t count, uint32_t index);
629 void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
630 uint32_t count, uint32_t index);
631 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
632 sPAPRMachineState *spapr);
633
634 /* rtas-configure-connector state */
635 struct sPAPRConfigureConnectorState {
636 uint32_t drc_index;
637 int fdt_offset;
638 int fdt_depth;
639 QTAILQ_ENTRY(sPAPRConfigureConnectorState) next;
640 };
641
642 void spapr_ccs_reset_hook(void *opaque);
643
644 void spapr_rtc_read(sPAPRRTCState *rtc, struct tm *tm, uint32_t *ns);
645 int spapr_rtc_import_offset(sPAPRRTCState *rtc, int64_t legacy_offset);
646
647 #define TYPE_SPAPR_RNG "spapr-rng"
648
649 int spapr_rng_populate_dt(void *fdt);
650
651 #define SPAPR_MEMORY_BLOCK_SIZE (1 << 28) /* 256MB */
652
653 /*
654 * This defines the maximum number of DIMM slots we can have for sPAPR
655 * guest. This is not defined by sPAPR but we are defining it to 32 slots
656 * based on default number of slots provided by PowerPC kernel.
657 */
658 #define SPAPR_MAX_RAM_SLOTS 32
659
660 /* 1GB alignment for hotplug memory region */
661 #define SPAPR_HOTPLUG_MEM_ALIGN (1ULL << 30)
662
663 /*
664 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
665 * property under ibm,dynamic-reconfiguration-memory node.
666 */
667 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
668
669 /*
670 * Defines for flag value in ibm,dynamic-memory property under
671 * ibm,dynamic-reconfiguration-memory node.
672 */
673 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
674 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
675 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
676
677 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
678
679 #endif /* HW_SPAPR_H */