spapr: Enable ISA 3.0 MMU mode selection via CAS
[qemu.git] / include / hw / ppc / spapr_ovec.h
1 /*
2 * QEMU SPAPR Option/Architecture Vector Definitions
3 *
4 * Each architecture option is organized/documented by the following
5 * in LoPAPR 1.1, Table 244:
6 *
7 * <vector number>: the bit-vector in which the option is located
8 * <vector byte>: the byte offset of the vector entry
9 * <vector bit>: the bit offset within the vector entry
10 *
11 * where each vector entry can be one or more bytes.
12 *
13 * Firmware expects a somewhat literal encoding of this bit-vector
14 * structure, where each entry is stored in little-endian so that the
15 * byte ordering reflects that of the documentation, but where each bit
16 * offset is from "left-to-right" in the traditional representation of
17 * a byte value where the MSB is the left-most bit. Thus, each
18 * individual byte encodes the option bits in reverse order of the
19 * documented bit.
20 *
21 * These definitions/helpers attempt to abstract away this internal
22 * representation so that we can define/set/test for individual option
23 * bits using only the documented values. This is done mainly by relying
24 * on a bitmap to approximate the documented "bit-vector" structure and
25 * handling conversations to-from the internal representation under the
26 * covers.
27 *
28 * Copyright IBM Corp. 2016
29 *
30 * Authors:
31 * Michael Roth <mdroth@linux.vnet.ibm.com>
32 *
33 * This work is licensed under the terms of the GNU GPL, version 2 or later.
34 * See the COPYING file in the top-level directory.
35 */
36 #ifndef _SPAPR_OVEC_H
37 #define _SPAPR_OVEC_H
38
39 #include "cpu.h"
40 #include "migration/vmstate.h"
41
42 typedef struct sPAPROptionVector sPAPROptionVector;
43
44 #define OV_BIT(byte, bit) ((byte - 1) * BITS_PER_BYTE + bit)
45
46 /* option vector 5 */
47 #define OV5_DRCONF_MEMORY OV_BIT(2, 2)
48 #define OV5_FORM1_AFFINITY OV_BIT(5, 0)
49 #define OV5_HP_EVT OV_BIT(6, 5)
50
51 /* ISA 3.00 MMU features: */
52 #define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */
53 #define OV5_MMU_RADIX_300 OV_BIT(24, 1) /* 1=Radix only, 0=Hash only */
54 #define OV5_MMU_RADIX_GTSE OV_BIT(26, 1) /* Radix GTSE */
55
56 /* interfaces */
57 sPAPROptionVector *spapr_ovec_new(void);
58 sPAPROptionVector *spapr_ovec_clone(sPAPROptionVector *ov_orig);
59 void spapr_ovec_intersect(sPAPROptionVector *ov,
60 sPAPROptionVector *ov1,
61 sPAPROptionVector *ov2);
62 bool spapr_ovec_diff(sPAPROptionVector *ov,
63 sPAPROptionVector *ov_old,
64 sPAPROptionVector *ov_new);
65 void spapr_ovec_cleanup(sPAPROptionVector *ov);
66 void spapr_ovec_set(sPAPROptionVector *ov, long bitnr);
67 void spapr_ovec_clear(sPAPROptionVector *ov, long bitnr);
68 bool spapr_ovec_test(sPAPROptionVector *ov, long bitnr);
69 sPAPROptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector);
70 int spapr_ovec_populate_dt(void *fdt, int fdt_offset,
71 sPAPROptionVector *ov, const char *name);
72
73 /* migration */
74 extern const VMStateDescription vmstate_spapr_ovec;
75
76 #endif /* !defined (_SPAPR_OVEC_H) */