ppx/xics: introduce a parent_reset in ICSStateClass
[qemu.git] / include / hw / ppc / xics.h
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #ifndef XICS_H
29 #define XICS_H
30
31 #include "hw/qdev.h"
32 #include "target/ppc/cpu-qom.h"
33
34 #define XICS_IPI 0x2
35 #define XICS_BUID 0x1
36 #define XICS_IRQ_BASE (XICS_BUID << 12)
37
38 /*
39 * We currently only support one BUID which is our interrupt base
40 * (the kernel implementation supports more but we don't exploit
41 * that yet)
42 */
43 typedef struct ICPStateClass ICPStateClass;
44 typedef struct ICPState ICPState;
45 typedef struct PnvICPState PnvICPState;
46 typedef struct ICSStateClass ICSStateClass;
47 typedef struct ICSState ICSState;
48 typedef struct ICSIRQState ICSIRQState;
49 typedef struct XICSFabric XICSFabric;
50
51 #define TYPE_ICP "icp"
52 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
53
54 #define TYPE_KVM_ICP "icp-kvm"
55 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
56
57 #define TYPE_PNV_ICP "pnv-icp"
58 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
59
60 #define ICP_CLASS(klass) \
61 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
62 #define ICP_GET_CLASS(obj) \
63 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
64
65 struct ICPStateClass {
66 DeviceClass parent_class;
67
68 DeviceRealize parent_realize;
69 DeviceReset parent_reset;
70
71 void (*pre_save)(ICPState *icp);
72 int (*post_load)(ICPState *icp, int version_id);
73 void (*synchronize_state)(ICPState *icp);
74 };
75
76 struct ICPState {
77 /*< private >*/
78 DeviceState parent_obj;
79 /*< public >*/
80 CPUState *cs;
81 ICSState *xirr_owner;
82 uint32_t xirr;
83 uint8_t pending_priority;
84 uint8_t mfrr;
85 qemu_irq output;
86
87 XICSFabric *xics;
88 };
89
90 #define ICP_PROP_XICS "xics"
91 #define ICP_PROP_CPU "cpu"
92
93 struct PnvICPState {
94 ICPState parent_obj;
95
96 MemoryRegion mmio;
97 uint32_t links[3];
98 };
99
100 #define TYPE_ICS_BASE "ics-base"
101 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
102
103 /* Retain ics for sPAPR for migration from existing sPAPR guests */
104 #define TYPE_ICS_SIMPLE "ics"
105 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
106
107 #define TYPE_ICS_KVM "icskvm"
108 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM)
109
110 #define ICS_BASE_CLASS(klass) \
111 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
112 #define ICS_BASE_GET_CLASS(obj) \
113 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
114
115 struct ICSStateClass {
116 DeviceClass parent_class;
117
118 DeviceRealize parent_realize;
119 DeviceReset parent_reset;
120
121 void (*pre_save)(ICSState *s);
122 int (*post_load)(ICSState *s, int version_id);
123 void (*reject)(ICSState *s, uint32_t irq);
124 void (*resend)(ICSState *s);
125 void (*eoi)(ICSState *s, uint32_t irq);
126 void (*synchronize_state)(ICSState *s);
127 };
128
129 struct ICSState {
130 /*< private >*/
131 DeviceState parent_obj;
132 /*< public >*/
133 uint32_t nr_irqs;
134 uint32_t offset;
135 qemu_irq *qirqs;
136 ICSIRQState *irqs;
137 XICSFabric *xics;
138 };
139
140 #define ICS_PROP_XICS "xics"
141
142 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
143 {
144 return (ics->offset != 0) && (nr >= ics->offset)
145 && (nr < (ics->offset + ics->nr_irqs));
146 }
147
148 struct ICSIRQState {
149 uint32_t server;
150 uint8_t priority;
151 uint8_t saved_priority;
152 #define XICS_STATUS_ASSERTED 0x1
153 #define XICS_STATUS_SENT 0x2
154 #define XICS_STATUS_REJECTED 0x4
155 #define XICS_STATUS_MASKED_PENDING 0x8
156 #define XICS_STATUS_PRESENTED 0x10
157 #define XICS_STATUS_QUEUED 0x20
158 uint8_t status;
159 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
160 #define XICS_FLAGS_IRQ_LSI 0x1
161 #define XICS_FLAGS_IRQ_MSI 0x2
162 #define XICS_FLAGS_IRQ_MASK 0x3
163 uint8_t flags;
164 };
165
166 struct XICSFabric {
167 Object parent;
168 };
169
170 #define TYPE_XICS_FABRIC "xics-fabric"
171 #define XICS_FABRIC(obj) \
172 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
173 #define XICS_FABRIC_CLASS(klass) \
174 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
175 #define XICS_FABRIC_GET_CLASS(obj) \
176 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
177
178 typedef struct XICSFabricClass {
179 InterfaceClass parent;
180 ICSState *(*ics_get)(XICSFabric *xi, int irq);
181 void (*ics_resend)(XICSFabric *xi);
182 ICPState *(*icp_get)(XICSFabric *xi, int server);
183 } XICSFabricClass;
184
185 #define XICS_IRQS_SPAPR 1024
186
187 void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle);
188
189 ICPState *xics_icp_get(XICSFabric *xi, int server);
190
191 /* Internal XICS interfaces */
192 void icp_set_cppr(ICPState *icp, uint8_t cppr);
193 void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
194 uint32_t icp_accept(ICPState *ss);
195 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
196 void icp_eoi(ICPState *icp, uint32_t xirr);
197
198 void ics_simple_write_xive(ICSState *ics, int nr, int server,
199 uint8_t priority, uint8_t saved_priority);
200
201 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
202 void icp_pic_print_info(ICPState *icp, Monitor *mon);
203 void ics_pic_print_info(ICSState *ics, Monitor *mon);
204
205 void ics_resend(ICSState *ics);
206 void icp_resend(ICPState *ss);
207
208 typedef struct sPAPRMachineState sPAPRMachineState;
209
210 int xics_kvm_init(sPAPRMachineState *spapr, Error **errp);
211 void xics_spapr_init(sPAPRMachineState *spapr);
212
213 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi,
214 Error **errp);
215
216 #endif /* XICS_H */