ppc/spapr: QOM'ify sPAPRRTCState
[qemu.git] / include / hw / ppc / xics.h
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
5 *
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27
28 #ifndef XICS_H
29 #define XICS_H
30
31 #include "hw/qdev.h"
32
33 #define XICS_IPI 0x2
34 #define XICS_BUID 0x1
35 #define XICS_IRQ_BASE (XICS_BUID << 12)
36
37 /*
38 * We currently only support one BUID which is our interrupt base
39 * (the kernel implementation supports more but we don't exploit
40 * that yet)
41 */
42 typedef struct ICPStateClass ICPStateClass;
43 typedef struct ICPState ICPState;
44 typedef struct ICSStateClass ICSStateClass;
45 typedef struct ICSState ICSState;
46 typedef struct ICSIRQState ICSIRQState;
47 typedef struct XICSFabric XICSFabric;
48
49 #define TYPE_ICP "icp"
50 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
51
52 #define TYPE_KVM_ICP "icp-kvm"
53 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
54
55 #define ICP_CLASS(klass) \
56 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
57 #define ICP_GET_CLASS(obj) \
58 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
59
60 struct ICPStateClass {
61 DeviceClass parent_class;
62
63 void (*pre_save)(ICPState *s);
64 int (*post_load)(ICPState *s, int version_id);
65 void (*cpu_setup)(ICPState *icp, PowerPCCPU *cpu);
66 };
67
68 struct ICPState {
69 /*< private >*/
70 DeviceState parent_obj;
71 /*< public >*/
72 CPUState *cs;
73 ICSState *xirr_owner;
74 uint32_t xirr;
75 uint8_t pending_priority;
76 uint8_t mfrr;
77 qemu_irq output;
78 bool cap_irq_xics_enabled;
79
80 XICSFabric *xics;
81 };
82
83 #define TYPE_ICS_BASE "ics-base"
84 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
85
86 /* Retain ics for sPAPR for migration from existing sPAPR guests */
87 #define TYPE_ICS_SIMPLE "ics"
88 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
89
90 #define TYPE_ICS_KVM "icskvm"
91 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM)
92
93 #define ICS_BASE_CLASS(klass) \
94 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
95 #define ICS_BASE_GET_CLASS(obj) \
96 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
97
98 struct ICSStateClass {
99 DeviceClass parent_class;
100
101 void (*realize)(DeviceState *dev, Error **errp);
102 void (*pre_save)(ICSState *s);
103 int (*post_load)(ICSState *s, int version_id);
104 void (*reject)(ICSState *s, uint32_t irq);
105 void (*resend)(ICSState *s);
106 void (*eoi)(ICSState *s, uint32_t irq);
107 };
108
109 struct ICSState {
110 /*< private >*/
111 DeviceState parent_obj;
112 /*< public >*/
113 uint32_t nr_irqs;
114 uint32_t offset;
115 qemu_irq *qirqs;
116 ICSIRQState *irqs;
117 XICSFabric *xics;
118 };
119
120 static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
121 {
122 return (ics->offset != 0) && (nr >= ics->offset)
123 && (nr < (ics->offset + ics->nr_irqs));
124 }
125
126 struct ICSIRQState {
127 uint32_t server;
128 uint8_t priority;
129 uint8_t saved_priority;
130 #define XICS_STATUS_ASSERTED 0x1
131 #define XICS_STATUS_SENT 0x2
132 #define XICS_STATUS_REJECTED 0x4
133 #define XICS_STATUS_MASKED_PENDING 0x8
134 uint8_t status;
135 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
136 #define XICS_FLAGS_IRQ_LSI 0x1
137 #define XICS_FLAGS_IRQ_MSI 0x2
138 #define XICS_FLAGS_IRQ_MASK 0x3
139 uint8_t flags;
140 };
141
142 struct XICSFabric {
143 Object parent;
144 };
145
146 #define TYPE_XICS_FABRIC "xics-fabric"
147 #define XICS_FABRIC(obj) \
148 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
149 #define XICS_FABRIC_CLASS(klass) \
150 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
151 #define XICS_FABRIC_GET_CLASS(obj) \
152 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
153
154 typedef struct XICSFabricClass {
155 InterfaceClass parent;
156 ICSState *(*ics_get)(XICSFabric *xi, int irq);
157 void (*ics_resend)(XICSFabric *xi);
158 ICPState *(*icp_get)(XICSFabric *xi, int server);
159 } XICSFabricClass;
160
161 #define XICS_IRQS_SPAPR 1024
162
163 int spapr_ics_alloc(ICSState *ics, int irq_hint, bool lsi, Error **errp);
164 int spapr_ics_alloc_block(ICSState *ics, int num, bool lsi, bool align,
165 Error **errp);
166 void spapr_ics_free(ICSState *ics, int irq, int num);
167 void spapr_dt_xics(int nr_servers, void *fdt, uint32_t phandle);
168
169 qemu_irq xics_get_qirq(XICSFabric *xi, int irq);
170 ICPState *xics_icp_get(XICSFabric *xi, int server);
171 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu);
172 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu);
173
174 /* Internal XICS interfaces */
175 int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
176
177 void icp_set_cppr(ICPState *icp, uint8_t cppr);
178 void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
179 uint32_t icp_accept(ICPState *ss);
180 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
181 void icp_eoi(ICPState *icp, uint32_t xirr);
182
183 void ics_simple_write_xive(ICSState *ics, int nr, int server,
184 uint8_t priority, uint8_t saved_priority);
185
186 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
187 void icp_pic_print_info(ICPState *icp, Monitor *mon);
188 void ics_pic_print_info(ICSState *ics, Monitor *mon);
189
190 void ics_resend(ICSState *ics);
191 void icp_resend(ICPState *ss);
192
193 typedef struct sPAPRMachineState sPAPRMachineState;
194
195 int xics_kvm_init(sPAPRMachineState *spapr, Error **errp);
196 int xics_spapr_init(sPAPRMachineState *spapr, Error **errp);
197
198 #endif /* XICS_H */