ppc/pnv: Add a HIOMAP erase command
[qemu.git] / include / hw / scsi / esp.h
1 #ifndef QEMU_HW_ESP_H
2 #define QEMU_HW_ESP_H
3
4 #include "hw/scsi/scsi.h"
5 #include "hw/sysbus.h"
6
7 /* esp.c */
8 #define ESP_MAX_DEVS 7
9 typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
10
11 #define ESP_REGS 16
12 #define TI_BUFSZ 16
13 #define ESP_CMDBUF_SZ 32
14
15 typedef struct ESPState ESPState;
16
17 enum pdma_origin_id {
18 PDMA,
19 TI,
20 CMD,
21 ASYNC,
22 };
23
24 struct ESPState {
25 uint8_t rregs[ESP_REGS];
26 uint8_t wregs[ESP_REGS];
27 qemu_irq irq;
28 qemu_irq irq_data;
29 uint8_t chip_id;
30 bool tchi_written;
31 int32_t ti_size;
32 uint32_t ti_rptr, ti_wptr;
33 uint32_t status;
34 uint32_t deferred_status;
35 bool deferred_complete;
36 uint32_t dma;
37 uint8_t ti_buf[TI_BUFSZ];
38 SCSIBus bus;
39 SCSIDevice *current_dev;
40 SCSIRequest *current_req;
41 uint8_t cmdbuf[ESP_CMDBUF_SZ];
42 uint32_t cmdlen;
43 uint32_t do_cmd;
44
45 /* The amount of data left in the current DMA transfer. */
46 uint32_t dma_left;
47 /* The size of the current DMA transfer. Zero if no transfer is in
48 progress. */
49 uint32_t dma_counter;
50 int dma_enabled;
51
52 uint32_t async_len;
53 uint8_t *async_buf;
54
55 ESPDMAMemoryReadWriteFunc dma_memory_read;
56 ESPDMAMemoryReadWriteFunc dma_memory_write;
57 void *dma_opaque;
58 void (*dma_cb)(ESPState *s);
59 uint8_t pdma_buf[32];
60 int pdma_origin;
61 uint32_t pdma_len;
62 uint32_t pdma_start;
63 uint32_t pdma_cur;
64 void (*pdma_cb)(ESPState *s);
65 };
66
67 #define TYPE_ESP "esp"
68 #define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
69
70 typedef struct {
71 /*< private >*/
72 SysBusDevice parent_obj;
73 /*< public >*/
74
75 MemoryRegion iomem;
76 MemoryRegion pdma;
77 uint32_t it_shift;
78 ESPState esp;
79 } SysBusESPState;
80
81 #define ESP_TCLO 0x0
82 #define ESP_TCMID 0x1
83 #define ESP_FIFO 0x2
84 #define ESP_CMD 0x3
85 #define ESP_RSTAT 0x4
86 #define ESP_WBUSID 0x4
87 #define ESP_RINTR 0x5
88 #define ESP_WSEL 0x5
89 #define ESP_RSEQ 0x6
90 #define ESP_WSYNTP 0x6
91 #define ESP_RFLAGS 0x7
92 #define ESP_WSYNO 0x7
93 #define ESP_CFG1 0x8
94 #define ESP_RRES1 0x9
95 #define ESP_WCCF 0x9
96 #define ESP_RRES2 0xa
97 #define ESP_WTEST 0xa
98 #define ESP_CFG2 0xb
99 #define ESP_CFG3 0xc
100 #define ESP_RES3 0xd
101 #define ESP_TCHI 0xe
102 #define ESP_RES4 0xf
103
104 #define CMD_DMA 0x80
105 #define CMD_CMD 0x7f
106
107 #define CMD_NOP 0x00
108 #define CMD_FLUSH 0x01
109 #define CMD_RESET 0x02
110 #define CMD_BUSRESET 0x03
111 #define CMD_TI 0x10
112 #define CMD_ICCS 0x11
113 #define CMD_MSGACC 0x12
114 #define CMD_PAD 0x18
115 #define CMD_SATN 0x1a
116 #define CMD_RSTATN 0x1b
117 #define CMD_SEL 0x41
118 #define CMD_SELATN 0x42
119 #define CMD_SELATNS 0x43
120 #define CMD_ENSEL 0x44
121 #define CMD_DISSEL 0x45
122
123 #define STAT_DO 0x00
124 #define STAT_DI 0x01
125 #define STAT_CD 0x02
126 #define STAT_ST 0x03
127 #define STAT_MO 0x06
128 #define STAT_MI 0x07
129 #define STAT_PIO_MASK 0x06
130
131 #define STAT_TC 0x10
132 #define STAT_PE 0x20
133 #define STAT_GE 0x40
134 #define STAT_INT 0x80
135
136 #define BUSID_DID 0x07
137
138 #define INTR_FC 0x08
139 #define INTR_BS 0x10
140 #define INTR_DC 0x20
141 #define INTR_RST 0x80
142
143 #define SEQ_0 0x0
144 #define SEQ_CD 0x4
145
146 #define CFG1_RESREPT 0x40
147
148 #define TCHI_FAS100A 0x4
149 #define TCHI_AM53C974 0x12
150
151 void esp_dma_enable(ESPState *s, int irq, int level);
152 void esp_request_cancelled(SCSIRequest *req);
153 void esp_command_complete(SCSIRequest *req, uint32_t status, size_t resid);
154 void esp_transfer_data(SCSIRequest *req, uint32_t len);
155 void esp_hard_reset(ESPState *s);
156 uint64_t esp_reg_read(ESPState *s, uint32_t saddr);
157 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val);
158 extern const VMStateDescription vmstate_esp;
159
160 #endif