block/export: Add query-block-exports
[qemu.git] / include / hw / ssi / stm32f2xx_spi.h
1 /*
2 * STM32F2XX SPI
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef HW_STM32F2XX_SPI_H
26 #define HW_STM32F2XX_SPI_H
27
28 #include "hw/sysbus.h"
29 #include "hw/ssi/ssi.h"
30 #include "qom/object.h"
31
32 #define STM_SPI_CR1 0x00
33 #define STM_SPI_CR2 0x04
34 #define STM_SPI_SR 0x08
35 #define STM_SPI_DR 0x0C
36 #define STM_SPI_CRCPR 0x10
37 #define STM_SPI_RXCRCR 0x14
38 #define STM_SPI_TXCRCR 0x18
39 #define STM_SPI_I2SCFGR 0x1C
40 #define STM_SPI_I2SPR 0x20
41
42 #define STM_SPI_CR1_SPE (1 << 6)
43 #define STM_SPI_CR1_MSTR (1 << 2)
44
45 #define STM_SPI_SR_RXNE 1
46
47 #define TYPE_STM32F2XX_SPI "stm32f2xx-spi"
48 OBJECT_DECLARE_SIMPLE_TYPE(STM32F2XXSPIState, STM32F2XX_SPI)
49
50 struct STM32F2XXSPIState {
51 /* <private> */
52 SysBusDevice parent_obj;
53
54 /* <public> */
55 MemoryRegion mmio;
56
57 uint32_t spi_cr1;
58 uint32_t spi_cr2;
59 uint32_t spi_sr;
60 uint32_t spi_dr;
61 uint32_t spi_crcpr;
62 uint32_t spi_rxcrcr;
63 uint32_t spi_txcrcr;
64 uint32_t spi_i2scfgr;
65 uint32_t spi_i2spr;
66
67 qemu_irq irq;
68 SSIBus *ssi;
69 };
70
71 #endif /* HW_STM32F2XX_SPI_H */